參數(shù)資料
型號(hào)： MC8610VT800GZ
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： MICROPROCESSOR, PBGA783
封裝： 29 X 29 MM, ROHS COMPLIANT, PLASTIC, FCBGA-783
文件頁(yè)數(shù)： 18/96頁(yè)
文件大?。?/td> 1237K
代理商： MC8610VT800GZ
Electrical Characteristics
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
25
2.4.5
Other Input Clocks
For information on the input clocks of other functional blocks of the platform such as SerDes see the specific section of this
document.
2.5
RESET Initialization
Table 12 describes the AC electrical specifications for the RESET initialization timing requirements of the MPC8610.
Table 13 provides the PLL lock times.
2.6
DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the MPC8610. Note that DDR
SDRAM is GVDD = 2.5 V and DDR2 SDRAM is GVDD = 1.8 V.
Table 12. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HRESET
100
—
μs
Minimum assertion time for SRESET
3
—
SYSCLKs
1
Platform PLL input setup time with stable SYSCLK before HRESET
negation
100
—
μs2
Input setup time for POR configs (other than PLL config) with respect to
negation of HRESET
4
—
SYSCLKs
1
Input hold time for all POR configs (including PLL config) with respect to
negation of HRESET
2
—
SYSCLKs
1
Maximum valid-to-high impedance time for actively driven POR configs
with respect to negation of HRESET
—
5
SYSCLKs
1
Notes:
1. SYSCLK is he primary clock input for the device.
2. This is related to HRESET assertion time.
Table 13. PLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
PLL lock times (platform, PCI and e600 core)
—
100
μs1
Notes:
1. The PLL lock time for the e600 core PLL requires an additional 255 platform clock cycles.
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相關(guān)代理商/技術(shù)參數(shù)
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MC8610VT800J 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications
MC861P 制造商:Motorola Inc 功能描述: 制造商:Texas Instruments 功能描述:
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