參數(shù)資料
型號： MC8610VT800GZ
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： MICROPROCESSOR, PBGA783
封裝： 29 X 29 MM, ROHS COMPLIANT, PLASTIC, FCBGA-783
文件頁數(shù)： 21/96頁
文件大?。?/td> 1237K
代理商： MC8610VT800GZ
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Electrical Characteristics
Freescale Semiconductor
28
Table 20 provides the input AC timing specifications for the DDR SDRAM when GVDD(typ)=2.5 V.
Table 21 provides the input AC timing specifications for the DDR SDRAM interface.
Figure 4 shows the DDR SDRAM input timing for the MDQS to MDQ skew measurement (tDISKEW).
Figure 4. DDR Input Timing Diagram for tDISKEW
Table 20. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface
At recommended operating conditions.
Parameter
Symbol
Min
Max
Unit
AC input low voltage
VIL
—MVREF – 0.31
V
AC input high voltage
VIH
MVREF + 0.31
—
V
Table 21. DDR SDRAM Input AC Timing Specifications
At recommended operating conditions.
Parameter
Symbol
Min
Max
Unit
Notes
Controller Skew for MDQS—MDQ/MECC
tCISKEW
ps
1, 2
533 MHz
400 MHz
333 MHz
–300
–365
–390
300
365
390
3
Notes:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
will be captured with MDQS[
n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be
determined by the following equation: tDISKEW = ±(T/4 – abs(tCISKEW)), where T is the clock period and abs(tCISKEW) is the
absolute value of tCISKEW.
3. Maximum DDR1 frequency is 400 MHz.
MCK[
n]
MCK[
n]
tMCK
MDQ[x]
MDQS[
n]
tDISKEW
D1
D0
tDISKEW
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相關(guān)代理商/技術(shù)參數(shù)
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MC8610VT800J 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications
MC861P 制造商:Motorola Inc 功能描述: 制造商:Texas Instruments 功能描述:
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