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參數(shù)資料
| 型號： | MC8610VT800GZ |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, PBGA783 |
| 封裝： | 29 X 29 MM, ROHS COMPLIANT, PLASTIC, FCBGA-783 |
| 文件頁數(shù)： | 70/96頁 |
| 文件大?。?/td> | 1237K |
| 代理商： | MC8610VT800GZ |
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MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Hardware Design Considerations
Freescale Semiconductor
72
Figure 47 provides the boundary-scan timing diagram.
Figure 47. Boundary-Scan Timing Diagram
3
Hardware Design Considerations
This section provides electrical and thermal design recommendations for successful application of the MPC8610.
3.1
System Clocking
This section describes the PLL configuration of the MPC8610. Note that the platform clock is identical to the internal MPX bus
clock.
This device includes six PLLs, as follows:
1.
The platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency ratio
between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as described in
2.
The e600 core PLL generates the core clock from the platform clock. The frequency ratio between the e600 core
clock and the platform clock is selected using the e600 PLL ratio configuration bits as described in Section 3.1.3,
3.
The PCI PLL generates the clocking for the PCI bus
4.
Each of the two SerDes blocks has a PLL.
VM = Midpoint Voltage (OVDD/2)
VM
tJTDVKH
tJTDXKH
Boundary
Data Outputs
Boundary
Data Outputs
JTAG
External Clock
Boundary
Data Inputs
Output Data Valid
tJTKLDX
tJTKLDZ
tJTKLDV
Input
Data Valid
Output Data Valid
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|---|---|
| MC8610VT800J | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
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