參數(shù)資料
型號: MC7447RX1267LB
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1267 MHz, RISC PROCESSOR, CBGA360
封裝: 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, FLIP CHIP, BGA-360
文件頁數(shù): 67/87頁
文件大?。?/td> 1586K
代理商: MC7447RX1267LB
MOTOROLA
MPC7457 RISC Microprocessor Hardware Specifications
7
Comparison with the MPC7455, MPC7445, MPC7450, MPC7451, and MPC7441
– Sleep—Power consumption is further reduced by disabling bus snooping, leaving only the
PLL in a locked and running state. All internal functional units are disabled.
– Deep sleep—When the part is in the sleep state, the system can disable the PLL. The system
can then disable the SYSCLK source for greater system power savings. Power-on reset
procedures for restarting and relocking the PLL must be followed on exiting the deep sleep
state.
— Thermal management facility provides software-controllable thermal management. Thermal
management is performed through the use of three supervisor-level registers and an
MPC7457-specific thermal management exception.
— Instruction cache throttling provides control of instruction fetching to limit power consumption
Performance monitor can be used to help debug system designs and improve software efficiency
In-system testability and debugging features through JTAG boundary-scan capability
Testability
— LSSD scan design
— IEEE 1149.1 JTAG interface
— Array built-in self test (ABIST)—factory test only
Reliability and serviceability
— Parity checking on system bus and L3 cache bus
— Parity checking on the L2 and L3 cache tag arrays
1.3
Comparison with the MPC7455, MPC7445,
MPC7450, MPC7451, and MPC7441
Table 1 compares the key features of the MPC7457 with the key features of the earlier MPC7455,
MPC7445, MPC7450, MPC7451, and MPC7441. To achieve a higher frequency, the number of logic levels
per cycle is reduced. Also, to achieve this higher frequency, the pipeline of the MPC7457 is extended
(compared to the MPC7400), while maintaining the same level of performance as measured by the number
of instructions executed per cycle (IPC).
Table 1. Microarchitecture Comparison
Microarchitectural Specs
MPC7457/MPC7447
MPC7455/MPC7445
MPC7450/MPC7451/
MPC7441
Basic Pipeline Functions
Logic inversions per cycle
18
Pipeline stages up to execute
5
Total pipeline stages (minimum)
7
Pipeline maximum instruction
throughput
3 + Branch
Pipeline Resources
Instruction buffer size
12
Completion buffer size
16
Renames (integer, float, vector)
16, 16, 16
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