參數(shù)資料
型號: MC7447RX1267LB
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1267 MHz, RISC PROCESSOR, CBGA360
封裝: 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, FLIP CHIP, BGA-360
文件頁數(shù): 58/87頁
文件大小: 1586K
代理商: MC7447RX1267LB
MOTOROLA
MPC7457 RISC Microprocessor Hardware Specifications
61
Document Revision History
1.10 Document Revision History
Table 21 provides a revision history for this hardware specification.
Table 21. Document Revision History
Revision
Number
Substantive Change(s)
0
Initial release.
1
Removed support for 1.5 V L3 interface voltage from Tables 3 and 4. 1.5 V I/O voltage is not
supported in current MPC7457 devices.
Added package thermal characteristics values to Table 5, made minor revisions to Section 1.9.8.
Added preliminary AC timing values to Tables 10 and 12.
Added footnotes to Table 17.
1.1
Nontechnical reformatting
2
Added substrate capacitor information in Sections 1.8.3 and 1.8.6.
Increased minimum processor and VCO frequencies in Table 8 from 500 MHz and 1000 MHz to 600
MHz and 1200 MHz (respectively).
Corrected maximum processor frequency for 1300 MHz devices in Table 8 (changed from 1333 MHz
to 1300 MHz).
Added value for to tL3CSKW1 Table 10.
Added L3OHCR information in Section 1.5.2.4.1.
Added values for tCO and tECI to Table 11.
Added Note 8 to Table 13 and Note 6 to Table 14.
Changed resistor value in PLL filter in Figure 24 from 10
to 400 .
Added 867 MHz speed grade.
Corrected Product Code in Tables 22 and 23.
Added pull-up/pull-down recommendations for CKSTP_IN and PLL_CFG[0:4] to Section 1.9.6.
3
Corrected numerous errors in lists of pins associated with tKHOV, tKHOX, tIVKH, and tIXKH in Table 9.
Added support for 1.5 V L3 interface voltage; issues fixed in Rev 1.1.
Corrected typos in Table 12.
Added data to Table 2.
Clarified address bus pull-up resistor recommendations in Section 1.9.6.
Modified Table 9, Figure 5, and Figure 6 to more accurately show when the mode select inputs
(BMODE[0:1], L3VSEL, BVSEL) are sampled and AC timing requirements
Table 10: Added skew and jitter values.
Table 14: Added AC timing values.
Table 23: Updated to reflect past and current part numbers not fully covered by this document.
Table 6: Removed CVIH and CVIL; VIH and VIL for SYSCLK input is the same as for other input signals,
and is now noted accordingly in this table.
Table 7: Removed Doze mode power entry (but left footnote 4 for clarity); documentation change only.
Nontechnical formatting
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PDF描述
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