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參數(shù)資料
| 型號(hào)： | MC7447RX1267LB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1267 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, FLIP CHIP, BGA-360 |
| 文件頁數(shù)： | 13/87頁 |
| 文件大?。?/td> | 1586K |
| 代理商： | MC7447RX1267LB |
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20
MPC7457 RISC Microprocessor Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
1.5.2.3
L3 Clock AC Specifications
The L3_CLK frequency is programmed by the L3 configuration register core-to-L3 divisor ratio. See
Table 18 for example core and L3 frequencies at various divisors. Table 10 provides the potential range of
L3_CLK output AC timing specifications as defined in Figure 7.
The maximum L3_CLK frequency is the core frequency divided by two. Given the high core frequencies
available in the MPC7457, however, most SRAM designs will be not be able to operate in this mode using
current technology and, as a result, will select a greater core-to-L3 divisor to provide a longer L3_CLK
period for read and write access to the L3 SRAMs. Therefore, the typical L3_CLK frequency shown in
Table 10 is considered to be the practical maximum in a typical system. The maximum L3_CLK frequency
for any application of the MPC7457 will be a function of the AC timings of the MPC7457, the AC timings
for the SRAM, bus loading, and printed-circuit board trace length, and may be greater or less than the value
given in Table 10. Note that SYSCLK input jitter and L3_CLK[0:1] output jitter are already comprehended
in the L3 bus AC timing specifications and do not need to be separately accounted for in an L3 AC timing
analysis. Clock skews, where applicable, do need to be accounted for in an AC timing analysis.
Motorola is similarly limited by system constraints and cannot perform tests of the L3 interface on a
socketed part on a functional tester at the maximum frequencies of Table 10. Therefore, functional operation
and AC timing information are tested at core-to-L3 divisors which result in L3 frequencies at 250 MHz or
lower.
Table 10. L3_CLK Output AC Timing Specifications
At recommended operating conditions. See Table 4.
Parameter
Symbol
All Speed Grades
Unit
Notes
Minimum
Typical
Maximum
L3 clock frequency
fL3_CLK
—
200
—
MHz
1
L3 clock cycle time
tL3_CLK
—5.0
—
ns
1
L3 clock duty cycle
tCHCL/tL3_CLK
—50
—
%
2
L3 clock output-to-output skew (L3_CLK0 to
L3_CLK1)
tL3CSKW1
—
100
ps
3
L3 clock output-to-output skew
(L3_CLK[0:1] to L3_ECHO_CLK[1,3])
tL3CSKW2
—
100
ps
4
L3 clock jitter
—
± 75
ps
5
Notes:
1. The maximum L3 clock frequency (and minimum L3 clock period) will be system dependent. See Section 1.5.2.3,
“L3 Clock AC Specifications,” for an explanation that this maximum frequency is not functionally tested at speed by
Motorola. The minimum L3 clock frequency and period are fSYSCLK and tSYSCLK, respectively.
2. The nominal duty cycle of the L3 output clocks is 50% measured at midpoint voltage.
3. Maximum possible skew between L3_CLK0 and L3_CLK1. This parameter is critical to the address and control
signals which are common to both SRAM chips in the L3.
4. Maximum possible skew between L3_CLK0 and L3_ECHO_CLK1 or between L3_CLK1 and L3_ECHO_CLK3 for
PB2 or Late Write SRAM. This parameter is critical to the read data signals because the processor uses the
feedback loop to latch data driven from the SRAM, each of which drives data based on L3_CLK0 or L3_CLK1.
5. Guaranteed by design and not tested. The input jitter on SYSCLK affects L3 output clocks and the L3 address, data,
and control signals equally and, therefore, is already comprehended in the AC timing and does not have to be
considered in the L3 timing analysis. The clock-to-clock jitter shown here is uncertainty in the internal clock period
caused by supply voltage noise or thermal effects. This is also comprehended in the AC timing specifications and
need not be considered in the L3 timing analysis.
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