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參數(shù)資料
| 型號： | MC7447RX1267LB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1267 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, FLIP CHIP, BGA-360 |
| 文件頁數(shù)： | 15/87頁 |
| 文件大小： | 1586K |
| 代理商： | MC7447RX1267LB |
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22
MPC7457 RISC Microprocessor Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
More specifically, certain signals within groups should be delay-matched with others in the same group
while intergroup routing is less critical. Only the address and control signals are common to both SRAMs
and additional timing margin is available for these signals. The double-clocked data signals are grouped
with individual clocks as shown in Figure 9 or Figure 11, depending on the type of SRAM. For example,
for the MSUG2 DDR SRAM (see Figure 9); L3DATA[0:31], L3DP[0:3], and L3_CLK[0] form a closely
coupled group of outputs from the MPC7457; while L3DATA[0:15], L3DP[0:1], and L3_ECHO_CLK[0]
form a closely coupled group of inputs.
The MPC7450 RISC Microprocessor Family User’s Manual refers to logical settings called ‘sample points’
used in the synchronization of reads from the receive FIFO. The computation of the correct value for this
setting is system-dependent and is described in the MPC7450 RISC Microprocessor Family User’s Manual.
Three specifications are used in this calculation and are given in Table 11. It is essential that all three
specifications are included in the calculations to determine the sample points, as incorrect settings can result
in errors and unpredictable behavior. For more information, see the MPC7450 RISC Microprocessor Family
User’s Manual.
1.5.2.4.1
Effects of L3OHCR Settings on L3 Bus AC Specifications
The AC timing of the L3 interface can be adjusted using the L3 Output Hold Control Register (L3OCHR).
Each field controls the timing for a group of signals. The AC timing specifications presented herein represent
the AC timing when the register contains the default value of 0x0000_0000. Incrementing a field delays the
associated signals, increasing the output valid time and hold time of the affected signals. In the special case
of delaying an L3_CLK signal, the net effect is to decrease the output valid and output hold times of all
signals being latched relative to that clock signal. The amount of delay added is summarized in Table 12.
Note that these settings affect output timing parameters only and do not impact input timing parameters of
the L3 bus in any way.
Table 11. Sample Points Calculation Parameters
Parameter
Symbol
Max
Unit
Notes
Delay from processor clock to internal_L3_CLK
tAC
3/4
tL3_CLK
1
Delay from internal_L3_CLK to L3_CLK[n] output pins
tCO
3ns
2
Delay from L3_ECHO_CLK[n] to receive latch
tECI
3ns
3
Notes:
1. This specification describes a logical offset between the internal clock edge used to launch the L3 address and
control signals (this clock edge is phase-aligned with the processor clock edge) and the internal clock edge used to
launch the L3_CLK[n] signals. With proper board routing, this offset ensures that the L3_CLK[n] edge will arrive at
the SRAM within a valid address window and provide adequate setup and hold time. This offset is reflected in the
L3 bus interface AC timing specifications, but must also be separately accounted for in the calculation of sample
points and, thus, is specified here.
2. This specification is the delay from a rising or falling edge on the internal_L3_CLK signal to the corresponding rising
or falling edge at the L3CLK[n] pins.
3. This specification is the delay from a rising or falling edge of L3_ECHO_CLK[n] to data valid and ready to be
sampled from the FIFO.
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