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參數(shù)資料
| 型號： | MC7447RX1267LB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1267 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, FLIP CHIP, BGA-360 |
| 文件頁數(shù)： | 49/87頁 |
| 文件大?。?/td> | 1586K |
| 代理商： | MC7447RX1267LB |
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MOTOROLA
MPC7457 RISC Microprocessor Hardware Specifications
53
System Design Information
1.9.6
Pull-Up/Pull-Down Resistor Requirements
The MPC7457 requires high-resistive (weak: 4.7-k
) pull-up resistors on several control pins of the bus
interface to maintain the control signals in the negated state after they have been actively negated and
released by the MPC7457 or other bus masters. These pins are: TS, ARTRY, SHDO, and SHD1.
Some pins designated as being for factory test must be pulled up to OVDD or down to GND to ensure proper
device operation. For the MPC7447, 360 BGA, the pins that must be pulled up to OVDD are: LSSD_MODE
and TEST[0:3]; the pins that must be pulled down to GND are: L1_TSTCLK and TEST[4]. For the
MPC7457, 483 BGA, the pins that must be pulled up to OVDD are: LSSD_MODE and TEST[0:5]; the pins
that must be pulled down are: L1_TSTCLK and TEST[6]. The CKSTP_IN signal should likewise be pulled
up through a pull-up resistor (weak or stronger: 4.7–1 k
) to prevent erroneous assertions of this signal.
In addition, the MPC7457 has one open-drain style output that requires a pull-up resistor (weak or stronger:
4.7–1 k
) if it is used by the system. This pin is CKSTP_OUT.
If pull-down resistors are used to configure BVSEL or L3VSEL, the resistors should be less than 250
(see
Table 16). Because PLL_CFG[0:4] must remain stable during normal operation, strong pull-up and
pull-down resistors (1 k
or less) are recommended to configure these signals in order to protect against
erroneous switching due to ground bounce, power supply noise or noise coupling.
During inactive periods on the bus, the address and transfer attributes may not be driven by any master and
may, therefore, float in the high-impedance state for relatively long periods of time. Because the MPC7457
must continually monitor these signals for snooping, this float condition may cause excessive power draw
by the input receivers on the MPC7457 or by other receivers in the system. These signals can be pulled up
through weak (10-k
) pull-up resistors by the system, address bus driven mode enabled (see the MPC7450
RISC Microprocessor Family Users’ Manual for more information about this mode), or they may be
otherwise driven by the system during inactive periods of the bus to avoid this additional power draw.
Preliminary studies have shown the additional power draw by the MPC7457 input receivers to be negligible
and, in any event, none of these measures are necessary for proper device operation. The snooped address
and transfer attribute inputs are: A[0:35], AP[0:4], TT[0:4], CI, WT, and GBL.
If extended addressing is not used, A[0:3] are unused and must be pulled low to GND through weak
pull-down resistors. If the MPC7457 is in 60x bus mode, DTI[0:3] must be pulled low to GND through weak
pull-down resistors.
The data bus input receivers are normally turned off when no read operation is in progress and, therefore,
do not require pull-up resistors on the bus. Other data bus receivers in the system, however, may require
pull-ups, or that those signals be otherwise driven by the system during inactive periods by the system. The
data bus signals are: D[0:63] and DP[0:7].
If address or data parity is not used by the system, and the respective parity checking is disabled through
HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and
should be left unconnected by the system. If all parity generation is disabled through HID0, all parity
checking should also be disabled through HID0, and all parity pins may be left unconnected by the system.
The L3 interface does not normally require pull-up resistors.
1.9.7
JTAG Configuration Signals
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specification, but is provided on all processors that implement the PowerPC architecture.
While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more
reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC7447RX600NB | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:PPC7457RX1000NB |
| MC7447RX733NB | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
| MC7447RX867NB | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:PPC7457RX1000NB |
| MC7448HX1000LC | 功能描述:IC MPU RISC 32BIT 360-FCCBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:MPC74xx 標準包裝:1 系列:MPC85xx 處理器類型:32-位 MPC85xx PowerQUICC III 特點:- 速度:1.2GHz 電壓:1.1V 安裝類型:表面貼裝 封裝/外殼:783-BBGA，F(xiàn)CBGA 供應商設備封裝:783-FCPBGA（29x29） 包裝:托盤 |
| MC7448HX1000LD | 功能描述:微處理器 - MPU APL8 RV2.2.1 1.15V 105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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