參數(shù)資料
型號： MC68L11F1CFN3
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, EEPROM, MICROCONTROLLER, PQCC68
封裝： PLASTIC, LCC-68
文件頁數(shù)： 18/174頁
文件大?。?/td> 981K
代理商： MC68L11F1CFN3
MOTOROLA
TIMING SYSTEM
MC68HC11F1
9-8
TECHNICAL DATA
All TOCx register pairs reset to ones ($FFFF).
9.3.2 Timer Compare Force Register
The CFORC register allows forced early compares. FOC[1:5] correspond to the five
output compares. These bits are set for each output compare that is to be forced. The
action taken as a result of a forced compare is the same as if there were a match be-
tween the OCx register and the free-running counter, except that the corresponding
interrupt status flag bits are not set. The forced channels trigger their programmed pin
actions to occur at the next timer count transition after the write to CFORC.
The CFORC bits should not be used on an output compare function that is pro-
grammed to toggle its output on a successful compare because a normal compare that
occurs immediately before or after the force can result in an undesirable operation.
FOC[1:5] — Force Output Comparison
When the FOC bit associated with an output compare circuit is set, the output compare
circuit immediately performs the action it is programmed to do when an output match
occurs.
0 = Not affected
1 = Output x action occurs
Bits [2:0] — Not implemented
Always read zero
9.3.3 Output Compare Mask Registers
Use OC1M with OC1 to specify the bits of port A that are affected by a successful OC1
compare. The bits of the OC1M register correspond to PA[7:3].
TOC1–TOC4 — Timer Output Compare
$1016–$101D
$1016
Bit 15
14
13
12
11
10
9
Bit 8
TOC1 (High)
$1017
Bit 7
654321
Bit 0
TOC1 (Low)
$1018
Bit 15
14
13
12
11
10
9
Bit 8
TOC2 (High)
$1019
Bit 7
654321
Bit 0
TOC2 (Low)
$101A
Bit 15
14
13
12
11
10
9
Bit 8
TOC3 (High)
$101B
Bit 7
654321
Bit 0
TOC3 (Low)
$101C
Bit 15
14
13
12
11
10
9
Bit 8
TOC4 (High)
$101D
Bit 7
654321
Bit 0
TOC4 (Low)
CFORC — Timer Compare Force
$100B
Bit 7
654321
Bit 0
FOC1
FOC2
FOC3
FOC4
FOC5
—
RESET:
0000000
0
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