參數(shù)資料
型號: MC68L11F1CFN3
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, EEPROM, MICROCONTROLLER, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 155/174頁
文件大?。?/td> 981K
代理商: MC68L11F1CFN3
MC68HC11F1
PARALLEL INPUT/OUTPUT
MOTOROLA
TECHNICAL DATA
6-1
SECTION 6 PARALLEL INPUT/OUTPUT
The MC68HC11F1 MCU has up to 54 input/output lines, depending on the operating
mode. The data bus of this microcontroller is nonmultiplexed. I/O lines are organized
into seven parallel ports. Ports with bidirectional pins have an associated data direc-
tion control register. This register (DDRx) contains a data direction control bit for each
bidirectional port line. The following table is a summary of the configuration and fea-
tures of each port.
Port pin function is mode dependent. Do not confuse pin function with the electrical
state of the pin at reset. Port pins are either driven to a specified logic level or are con-
figured as high impedance inputs. I/O pins configured as high-impedance inputs have
port data that is indeterminate. The contents of the corresponding latches are depen-
dent upon the electrical state of the pins during reset. In port descriptions, an “I” indi-
cates this condition. Port pins that are driven to a known logic level during reset are
shown with a value of either one or zero. Some control bits are unaffected by reset.
Reset states for these bits are indicated with a “U”.
6.1 Port A
Port A has eight bidirectional I/O pins and shares functions with the timer system.
Table 6-1 I/O Port Configuration
Port
Input Pins
Output Pins
Bidirectional Pins
Shared Functions
Port A
8
Timer
Port B
8
High-Order Address
Port C
8
Data Bus
Port D
6
SCI and SPI
Port E
8
A/D Converter
Port F
8
Low-Order Address
Port G
8
Chip Select Outputs
PORTA — Port A Data
$1000
Bit 7
654321
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
RESET:
IIIIIII
I
Alt. Pin
Func.:
PAI
OC2
OC3
OC4
IC4/OC5
IC1
IC2
IC3
And/or:
OC1
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