參數(shù)資料
型號: MC68L11F1CFN3
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, EEPROM, MICROCONTROLLER, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 143/174頁
文件大?。?/td> 981K
代理商: MC68L11F1CFN3
MOTOROLA
RESETS AND INTERRUPTS
MC68HC11F1
5-8
TECHNICAL DATA
SMOD — Special Mode Select
Can be read any time. Can only be written in special modes (SMOD = 1). Can only be
for more information.
MDA — Mode Select A
Can be read any time. Can only be written in special modes (SMOD = 1). Refer to
IRV — Internal Read Visibility
The IRV control bit allows internal read accesses to be available on the external data
bus during operation in expanded modes. In special modes (SMOD = 1), IRV resets
to one (enabled) and can be written any time. In normal modes (SMOD = 0), IRV re-
sets to zero (disabled) and only one write is allowed.
PSEL[3:0] — Priority Select Bits
These bits select one interrupt source to be elevated above all other I-bit-related
sources and can only be written while the I bit in the CCR is set (interrupts disabled).
5.4 Interrupts
The MCU has 18 interrupt vectors that support 22 interrupt sources. The 15 maskable
interrupts are generated by on-chip peripheral systems. These interrupts are recog-
nized when the global interrupt mask bit (I) in the condition code register (CCR) is
clear. The three non-maskable interrupt sources are illegal opcode trap, software in-
terrupt, and XIRQ pin. Refer to Table 5-4, which shows the interrupt sources and vec-
tor assignments for each source.
Table 5-3 Highest Priority Interrupt Selection
PSEL3
PSEL2
PSEL1
PSEL0
Interrupt Source Promoted
0000
Timer Overflow
0001
Pulse Accumulator Overflow
0010
Pulse Accumulator Input Edge
0011
SPI Serial Transfer Complete
0100
SCI Serial System
0101
Reserved (Default to IRQ)
0110
IRQ
0111
Real-Time Interrupt
1000
Timer Input Capture 1
1001
Timer Input Capture 2
1010
Timer Input Capture 3
1011
Timer Output Compare 1
1100
Timer Output Compare 2
1101
Timer Output Compare 3
1110
Timer Output Compare 4
1111
Timer Output Compare 5/Input Capture 4
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