參數(shù)資料
型號: MC68L11F1CFN3
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, EEPROM, MICROCONTROLLER, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 121/174頁
文件大小: 981K
代理商: MC68L11F1CFN3
MOTOROLA
OPERATING MODES AND ON-CHIP MEMORY
MC68HC11F1
4-12
TECHNICAL DATA
ADPU — A/D Power-Up
0 = A/D system disabled
1 = A/D system power enabled
CSEL — Clock Select
Selects alternate clock source for on-chip EEPROM and A/D charge pumps. On-chip
RC clock should be used when E clock falls below 1 MHz. Refer to SECTION 10 AN-
0 = A/D and EEPROM use system E clock
1 = A/D and EEPROM use internal RC clock
IRQE — Congure IRQ for Falling Edge-Sensitive Operation
0 = Low level-sensitive operation.
1 = Falling edge-sensitive only operation.
DLY — Enable Oscillator Start-up Delay
0 = The oscillator start-up delay coming out of STOP is bypassed and the MCU re-
sumes processing within about four bus cycles.
1 = A delay of approximately 4000 E-clock cycles is imposed as the MCU is started
up from the STOP power-saving mode.
CME — Clock Monitor Enable
In order to use both STOP and clock monitor, the CME bit must be written to zero be-
fore executing STOP, then written to one after recovering from STOP. Refer to SEC-
0 = Clock monitor disabled
1 = Clock monitor enabled
FCME — Force Clock Monitor Enable
When FCME equals one, slow or stopped clocks will cause a clock failure reset. To
use STOP mode, FCME must always equal zero. Refer to SECTION 5 RESETS AND
0 = Clock monitor follows state of CME bit
1 = Clock monitor enabled and cannot be disabled until next reset
CR[1:0] — COP Timer Rate Select Bits
These control bits determine a scaling factor for the watchdog timer. Refer to SEC-
4.3.2.4 OPT2 Register
The system configuration options 2 register (OPT2) controls three additional system
options.
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