參數(shù)資料
型號: MC68HC912BL16FU8
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64
封裝: QFP-64
文件頁數(shù): 89/128頁
文件大小: 3326K
代理商: MC68HC912BL16FU8
MC68HC912BL16TS/D
63
Read and write in special mode. Bits 0-3 not writable.
TSTSMD — Test Mode of Slow Mode Divider
0 = Not in Test Mode.
1 = Test slow divider. Internal divider states stored in TSTOUT[3:0]
BCSS— Bus Clock Select Slow
0 = SYSCLK is derived from crystal clock EXTALi.
1 = SYSCLK is derived from Slow clock SLWCLK only in special mode.
When TSTSMD set, TSTOUT[3:0] shows the Slow Mode counter. Bits are not writable.
10.6 Clock Divider Chains
Figure 13, Figure 14, Figure 15, and Figure 16 summarize the clock divider chains for the various pe-
ripherals on the MC68HC912BL16.
The “intwai” signal in Figure 13, or wait mode, is the only mechanism for choosing slow clocks versus
normal frequency clocks in normal operating modes.
0
1
0
1
10
800 KHz
400 KHz
200 KHz
0
1
0
12
667 KHz
333 KHz
167 KHz
0
1
14
571 KHz
286 KHz
143 KHz
1
0
16
500 KHz
250 KHz
125 KHz
1
0
1
18
444 KHz
222 KHz
111 KHz
1
0
1
0
20
400 KHz
200 KHz
100 KHz
1
0
1
22
364 KHz
182 KHz
91 KHz
1
0
24
333 KHz
167 KHz
84 KHz
1
0
1
26
308 KHz
154 KHz
77 KHz
1
0
28
286 KHz
143 KHz
72 KHz
1
30
267 KHz
133 KHz
67 KHz
CGTCFG — Clock Generator Test Register
$00E1
Bit 7
6
5
4
3
2
1
Bit 0
TSTSMD
BCSS
0
TSTOUT3 TSTOUT2 TSTOUT1 TSTOUT0
RESET:
0
Table 22 SLOW Mode Register Divider Rates
SLDV3 SLDV2 SLDV1 SLDV0
Divide By:
(SLOW * 2)
Bus Rate w/
16MHz XTAL
Bus Rate w/
8MHz XTAL
Bus Rate w/
4MHz XTAL
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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