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| 型號(hào)： | MC68HC912BL16FU8 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數(shù)： | 70/128頁 |
| 文件大小： | 3326K |
| 代理商： | MC68HC912BL16FU8 |
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MC68HC912BL16
46
MC68HC912BL16TS/D
7.8 Program/Erase Protection Interlocks
The Flash EEPROM program and erase mechanisms provide maximum protection from accidental pro-
gramming or erasure.
The voltage required to program/erase the Flash EEPROM (VFP) is supplied via an external pin. If VFP
is not present, no programming/erasing will occur. Furthermore, the program/erase voltage will not be
applied to the Flash EEPROM unless turned on by setting a control bit (ENPE). The ENPE bit may not
be set unless the programming address and data latches have been written previously with a valid ad-
dress. The latches may not be written unless enabled by setting a control bit (LAT). The LAT and ENPE
control bits must be written on separate writes to the control register (FEECTL) and must be separated
by a write to the programming latches. The ERAS and LAT bits are also protected when ENPE is set.
This prevents inadvertent switching between erase/program mode and also prevents the latched data
and address from being changed after a program cycle has been initiated.
7.9 Stop or Wait Mode
When stop or wait commands are executed, the MCU puts the Flash EEPROM in stop or wait mode. In
these modes the Flash module will cease erasure or programming immediately. It is advised not to enter
stop or wait modes when programming the Flash array.
CAUTION
The Flash EEPROM module is not able to recover from STOP without a 1 micro-
second delay. This cannot be controlled internal to the MCU. Therefore, do not at-
tempt to recover from STOP with an interrupt. Use RESET to recover from a STOP
mode executed from Flash EEPROM. Recovery from a STOP instruction executed
from EEPROM and RAM operate normally.
7.10 Test Mode
The Flash EEPROM has some special test functions which are only accessible when the device is in
test mode. Test mode is indicated to the Flash EEPROM module when the SMOD line on the LIB is
asserted. When SMOD is asserted, the special test control bits may be accessed via the LIB to invoke
the special test functions in the Flash EEPROM module. When SMOD is not asserted, writes to the test
control bits have no effect and all bits in the test register FEETST will be cleared. This ensures that
Flash EEPROM test mode cannot be invoked inadvertently during normal operation.
Note that the Flash EEPROM module will operate normally, even if SMOD is asserted, until a special
test function is invoked. The test mode adds additional features over normal mode which allow the tests
to be performed even after the device is installed in the final product.
7.11 FLASH Program/Erase Voltage Signal Conditioning
A voltage of at least VDD – 0.35 V must be applied at all times to the VFPE pins; or damage to the
FLASH module can occur. FLASH modules can be damaged by power-on and power off VFPE
transients. VFPE must not rise to programming level while VDD is below specified minimum value,
and must not fall below minimum specified value while VDD is applied. Figure 9 shows the VFPE
and VDD operating envelope.
Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for
maximum and operating voltage specifications.
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For More Information On This Product,
Go to: www.freescale.com
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