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參數(shù)資料
| 型號： | MC68HC912BL16FU8 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數(shù)： | 102/128頁 |
| 文件大?。?/td> | 3326K |
| 代理商： | MC68HC912BL16FU8 |
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MC68HC912BL16TS/D
75
PSBCK — PWM Stops while in Background Mode
0 = Allows PWM to continue while in background mode.
1 = Disable PWM input clock when the part is in background mode.
Read anytime but write only in special mode (SMODN = 0). These bits are available only in special
mode and are reset in normal mode.
The PWM has some special test functions which are only accessible when the device is in Special
Mode. Special Mode is indicated to the PWM module when the SMOD line on the LIB is asserted.
When the SMOD line is asserted, the Special Mode register control bits are accessed via the LIB. When
SMOD is not asserted, writes to the Special Mode control bits have no effect and all bits in the Special
Mode register are forced to 0. This ensures that the PWM Special Mode can not be invoked inadvert-
ently during normal operation.
DISCR — Disable Reset of Channel Counter on Write to Channel Counter
0 = Normal operation. Write to PWM channel counter will reset channel counter.
1 = Write to PWM channel counter does not reset channel counter.
DISCP — Disable Compare Count Period
0 = Normal operation
1 = In left-aligned output mode, match of the period does not reset the associated PWM counter
register.
DISCAL — Disable Load of Scale-Counters on Write to the Associated Scale Registers
0 = Normal operation
1 = Write to PWSCAL0 and PWSCAL1 does not load scale counters
PWM functions share port P pins 3 to 0 and take precedence over the general-purpose port when en-
abled. PORTP can be read anytime. When configured as input, a read will return the pin level. When
configured as output, a read will return the latched output data.
A write will drive associated pins only if configured for output and the corresponding PWM channel is
not enabled.
After reset, all pins are general-purpose, high-impedance inputs.
NOTE
Writes do not change pin state when pin is configured for PWM outputs, only after
the PWM channel becomes available on port P pin, see PWEN bit description.
PWTST — PWM Special Mode Register (“Test”)
$0055
Bit 7
6
5
4
3
2
1
Bit 0
DISCR
DISCP
DISCAL
0
RESET:
0
PORTPP — Port P Data Register
$0056
Bit 7
6
5
4
3
2
1
Bit 0
PP7
PP6
PP5
PP4
PP3
PP2
PP1
PP0
PWM
–
PWM3
PWM2
PWM1
PWM0
RESET:
–
PORTPD — Port P Data Direction Register
$0057
Bit 7
6
5
4
3
2
1
Bit 0
DDP7
DDP6
DDP5
DDP4
DDP3
DDP2
DDP1
DDP0
RESET:
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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