參數(shù)資料
型號: MC68HC912BL16FU8
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64
封裝: QFP-64
文件頁數(shù): 108/128頁
文件大?。?/td> 3326K
代理商: MC68HC912BL16FU8
MC68HC912BL16
80
MC68HC912BL16TS/D
1 = For TFLG1($8E), a read from an input capture or a write to the output compare channel ($90–
$9F) causes the corresponding channel flag, CnF, to be cleared. For TFLG2 ($8F), any access
to the TCNT register ($84, $85) clears the TOF flag. Any access to the PACNT register ($A2,
$A3) clears the PAOVF and PAIF flags in the PAFLG register ($A1). This has the advantage of
eliminating software overhead in a separate clear sequence. Extra care is required to avoid ac-
cidental flag clearing due to unintended accesses.
Read or write anytime.
NOTE
Port T[6] is not bonded to any pin in MC68HC912BL16.
OMn — Output Mode
OLn — Output Level
These eight pairs of control bits are encoded to specify the output action to be taken as a result of a
successful OCn compare. When either OMn or OLn is one, the pin associated with OCn becomes an
output tied to OCn regardless of the state of the associated DDRT bit.
TQCR — Reserved
$0087
Bit 7
6
5
4
3
2
1
Bit 0
0
RESET:
0
TCTL1 — Timer Control Register 1
$0088
Bit 7
6
5
4
3
2
1
Bit 0
OM7
OL7
OM6
OL6
OM5
OL5
OM4
OL4
RESET:
0
TCTL2 — Timer Control Register 2
$0089
Bit 7
6
5
4
3
2
1
Bit 0
OM3
OL3
OM2
OL2
OM1
OL1
OM0
OL0
RESET:
0
Table 25 Compare Result Output Action
OMn
OLn
Action
0
Timer disconnected from output pin logic
0
1
Toggle OCn output line
1
0
Clear OCn output line to zero
1
Set OCn output line to one
TCTL3 — Timer Control Register 3
$008A
Bit 7
6
5
4
3
2
1
Bit 0
EDG7B
EDG7A
EDG6B
EDG6A
EDG5B
EDG5A
EDG4B
EDG4A
RESET:
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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