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參數(shù)資料
| 型號： | MC68HC912BL16FU8 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數(shù)： | 58/128頁 |
| 文件大?。?/td> | 3326K |
| 代理商： | MC68HC912BL16FU8 |
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MC68HC912BL16TS/D
35
In special single-chip mode, the E clock is enabled as a timing reference and the other bits of port E are
configured for general-purpose I/O.
In normal expanded modes, the reset vector is located in external memory. The E clock may be required
for this access but R/W is only needed by the system when there are external writable resources. There-
fore in normal expanded modes, only the E clock is configured for its alternate bus control function and
the other bits of port E are configured for general-purpose I/O. If the normal expanded system needs
any other bus-control signals, PEAR would need to be written before any access that needed the addi-
tional signals.
In special expanded modes, IPIPE1, IPIPE0, E, R/W, and LSTRB are configured as bus-control signals.
In peripheral mode, the PEAR register is not accessible for reads or writes.
NDBE — No Data Bus Enable
Read and write anytime.
0 = PE7 is used for external control of data enables on memories.
1 = PE7 is used for general-purpose I/O.
PIPOE — Pipe Signal Output Enable
Normal: write once; Special: write anytime except the first time. Read anytime. This bit has no effect in
single chip modes.
0 = PE[6:5] are general-purpose I/O.
1 = PE[6:5] are outputs and indicate the state of the instruction queue.
NECLK — No External E Clock
In expanded modes, writes to this bit have no effect. E clock is required for de-multiplexing the external
address; NECLK will remain zero in expanded modes. NECLK can be written once in normal single-
chip mode and can be written anytime in special single chip mode. The bit can be read anytime.
0 = PE4 is the external E-clock pin subject to the following limitation: In single-chip modes, PE4 is
general-purpose I/O unless NECLK = 0 and either IVIS = 1 or ESTR = 0. A 16-bit write to
PEAR:MODE can configure all three bits in one operation.
1 = PE4 is a general-purpose I/O pin.
LSTRE — Low Strobe (LSTRB) Enable
Normal: write once; Special: write anytime except the first time. Read anytime. This bit has no effect in
single-chip modes or normal expanded narrow mode.
0 = PE3 is a general-purpose I/O pin.
1 = PE3 is configured as the LSTRB bus-control output, provided the MCU is not in single chip or
normal expanded narrow modes.
LSTRB is used during external writes. After reset in normal expanded mode, LSTRB is disabled. If
needed, it should be enabled before external writes. External reads do not normally need LSTRB be-
cause all 16 data bits can be driven even if the MCU only needs eight bits of data.
TAGLO is a shared function of the PE3/LSTRB pin. In special expanded modes with LSTRE set and the
BDM instruction tagging on, a zero at the falling edge of E tags the instruction word low byte being read
into the instruction queue.
RDWE — Read/Write Enable
Normal: write once; Special: write anytime except the first time. Read anytime. This bit has no effect in
single-chip modes.
0 = PE2 is a general-purpose I/O pin.
1 = PE2 is configured as the R/W pin. In single-chip modes, RDWE has no effect and PE2 is a gen-
eral-purpose I/O pin.
R/W is used for external writes. After reset in normal expanded mode, it is disabled. If needed it should
be enabled before any external writes.
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