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參數(shù)資料
| 型號： | MC68HC912BL16FU8 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數(shù)： | 84/128頁 |
| 文件大?。?/td> | 3326K |
| 代理商： | MC68HC912BL16FU8 |
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MC68HC912BL16TS/D
59
10 Clock Functions
Clock generation circuitry generates the internal and external E-clock signals as well as internal clock
signals used by the CPU and on-chip peripherals. A clock monitor circuit, a computer operating properly
(COP) watchdog circuit, and a periodic interrupt circuit are also incorporated into the MC68HC912BL16.
10.1 Clock Sources
A compatible external clock signal can be applied to the EXTAL pin or the MCU can generate a clock
signal using an on-chip oscillator circuit and an external crystal or ceramic resonator. The MCU uses
three types of internal clock signals derived from the primary clock signal: T clocks, E clock, and P clock.
The T clocks are used by the CPU. The E and P clocks are used by the bus interfaces, BDM, SPI, and
ATD. The P clock also drives on-chip modules such as the timer chain, SCI, RTI, COP, and restart-from-
stop delay time. Figure 12 shows clock timing relationships.
Figure 12 Internal Clock Relationships
10.2 Computer Operating Properly (COP)
The COP or watchdog timer is an added check that a program is running and sequencing properly.
When the COP is being used, software is responsible for keeping a free-running watchdog timer from
timing out. If the watchdog timer times out it is an indication that the software is no longer being execut-
ed in the intended sequence; thus a system reset is initiated. Three control bits allow selection of seven
COP time-out periods or COP disable. When COP is enabled, sometime during the selected period the
program must write $55 and $AA (in this order) to the COPRST register. If the program fails to do this
the part will reset. If any value other than $55 or $AA is written to COPRST, the part is reset.
10.3 Real-Time Interrupt
There is a real-time (periodic) interrupt available to the user. This interrupt will occur at one of seven
selected rates. An interrupt flag and an interrupt enable bit are associated with this function. There are
three bits for the rate select.
10.4 Clock Monitor
The clock monitor circuit is based on an internal resistor-capacitor (RC) time delay. If no MCU clock
edges are detected within this RC time delay, the clock monitor can optionally generate a system reset.
The clock monitor function is enabled/disabled by the CME control bit in the COPCTL register. This
time-out is based on an RC delay so that the clock monitor can operate without any MCU clocks.
Clock monitor time-outs are shown in Table 19.
T1CLK
T2CLK
T3CLK
T4CLK
INT ECLK
PCLK
HC12B32 CLOCK RELATIONS
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