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參數(shù)資料
| 型號(hào)： | MC68HC711G5CFN |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁(yè)數(shù)： | 47/195頁(yè) |
| 文件大小： | 1940K |
| 代理商： | MC68HC711G5CFN |
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EVENT COUNTER
11-10
The only difference between this mode and mode 1 lies in the clock source used to drive the counter
in the PA unit (EVCNT2). In mode 1, the clock signal comes via the INPUT1 selector and is either
derived from the E-clock (gated or ungated) or an external signal. In mode 2, the signal which results
from a successful comparison between EVCNT1 and ECMP1A in the PWM unit is used to drive
EVCNT2 in the PA unit. This is the same signal which clears EVCNT1, thereby ending the PWM
period. EVCNT2, therefore, counts the number of periods completed by the PWM unit.
11.4.1
Operation of Pulse Width Modulation Unit in Mode 2
The PWM unit can be clocked by the E-clock, a scaled E-clock, or an external signal applied to the
EVI1 (PH5) pin. Alternatively an external signal on EVI1 can be used to gate the E-clock or scaled
E-clock signal to the counter EVCNT1. The clock source is selected via the INPUT1 selector.
The period of the PWM output signal is stored in ECMP1A. When a match occurs between this
compare register and the counter register, EVCNT1, the output unit EVO is reset, EVCNT1 is
cleared (to zero) and EVCNT2 in the PA is incremented by one. At the same time, an interrupt signal
EVENT1 is generated which, if enabled, interrupts the CPU.
The duty cycle of the PWM output signal is stored in ECMP1B. When a match occurs between this
compare register and EVCNT1, the PWM output signal changes state (from zero to one or from one
to zero depending on the polarity selected by the output unit.
DUTY CYCLE = 100 x [1 - (ECMP1B)/(ECMP1A)] %
The PWM unit will also work as a pulse accumulator by switching off the output signal to the EVO
pin (PH6) and ignoring ECMP1B.
11.4.2
Operation of Pulse Accumulator Unit in Mode 2
The PA unit is clocked each time there is a successful comparison between EVCNT1 and ECMP1A
in the PWM unit, i.e. at the end of each PWM period.
EVCNT2 counts the pulses coming from the PWM unit. It is cleared by a successful comparison
between itself and the compare register ECMP2A. ECMP2A can be programmed with any 8-bit
value to control the time when the counter is cleared.
ECMP2B can be used to generate an interrupt signal EVENT2 after a required number of input
pulses have been accumulated by EVCNT2. If enabled, EVENT2 will interrupt the CPU.
11.4.3
Register Functions in Mode 2
11.4.3.1
Counter 1 (EVCNT1)
EVCNT1 counts the number of pulses coming from the INPUT1 selector. It is cleared by a successful
comparison between itself and ECMP1A.
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For More Information On This Product,
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