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參數(shù)資料
| 型號： | MC68HC711G5CFN |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 149/195頁 |
| 文件大?。?/td> | 1940K |
| 代理商： | MC68HC711G5CFN |
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RESETS, INTERRUPTS AND LOW POWER MODES
5-5
mode). Port C is initialized as an input port (DDRC = $00). Ports B and F are general purpose output
ports with all bits initialized to zero. R/W outputs a logic high level all the time. Ports A, D, G, H, and
J are configured as general purpose high-impedance inputs. Port E pins are configured as inputs.
Timer — The timer system is initialized during reset to a count of $0000. The prescaler bits are
cleared (to zero) so that the count rate equals the E-clock rate. All output compare registers are
initialized to $FFFF to guarantee the maximum time before any successful compare. All input
capture registers are indeterminate after reset. The OC1M register is cleared so successful OC1
compares will not affect any I/O pins. The other output compare functions are configured so as not
to affect any I/O pins on successful compares. All input capture edge detector circuits are configured
for “capture disabled” operation. The timer overflow interrupt flag and all timer function interrupt flags
are cleared and all timer interrupts are disabled by their mask bits being cleared.
Real Time Interrupt — The real time interrupt flag is cleared and automatic hardware interrupts are
masked by the RTII bit being clear. The rate control bits RTR1, RTR0 are cleared to zero, thus
selecting the shortest real time interrupt period.
Pulse Accumulator — The pulse accumulator system is disabled at reset. The PAIF and PAOVF
flags are cleared to indicate no pulse accumulator interrupts pending. The PAII and PAOVI interrupt
enable bits are cleared to inhibit pulse accumulator interrupts.
COP — The COP watchdog system is enabled if the NOCOP control bit is a zero and disabled if
NOCOP is one. The COP rate is set for the shortest duration timeout. If a different rate is required
then it must be initialized within 64 E-clock cycles after reset.
SCI Serial I/O — The reset condition of the SCI system is independent of the operating mode. At
reset, the SCI baud rate is indeterminate and must be established by a software write to the BAUD
register (note that in bootstrap mode software in the bootstrap ROM initializes the SCI system and
the baud rate). The frame format is configured for 8-bit data (M = 0). All transmit and receive
interrupts are masked and both the transmitter and receiver are disabled (turned off) so the port pins
associated with the SCI default to being general purpose I/O lines. The send break and receiver
wake-up functions are disabled. Although the wake-up function is disabled (RWU = 0), the WAKE
control bit is initialized to 0, thus selecting the ‘idle line’ mode of wake-up. The TDRE and TC status
bits are both set to one indicating that there is no transmit data in either the transmit data register
or the transmit serial shift register. The receiver related status bits RDRF, IDLE, OR, NF, and FE
are all cleared by reset.
SPI Serial I/O — The SPI system is disabled during reset. The port pins associated with this function
default to being general purpose I/O pins.
A to D — The A/D system is disabled by reset. Both the ADPU and CSEL bits are cleared to zero,
disabling the analog circuitry of the A/D and the internal R-C oscillator. The bits in the ADCTL control
register are indeterminate following reset. In any case, a write must be performed to this register in
order to initiate a conversion sequence.
System — The “Highest Priority I” interrupt defaults to the external interrupt pin IRQ by PSEL4 –
PSEL0 being set equal to 00110. The RBOOT, SMOD, and MDA bits in the HPRIO register reflect
the status of the MODB and MODA inputs at the rising edge of reset. The internal read visibility
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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