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參數(shù)資料
| 型號： | MC68HC711G5CFN |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 166/195頁 |
| 文件大?。?/td> | 1940K |
| 代理商： | MC68HC711G5CFN |
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PROGRAMMABLE TIMER
6-2
6.1.2
Prescalers
There are two prescalers, one for each of the timer counters. All of the prescaler select bits are
included in one register (TPRE). This allows the user to set both prescalers simultaneously so that
both counters may be kept synchronized. The external clock edge selects for counter 2 are also
included in this register.
Each prescaler is a 3-stage divider with the E-clock as its input, and each stage divides by two. The
prescaler output is selectable as E, E/2, E/4, or E/8. After reset, the MC68HC11G5 is configured to
use the E-clock as the input to both counters. Initialization software may optionally reconfigure
counter 1 to use one of the three prescale taps so that the E-clock is divided by 2, 4, or 8 before driving
the free running counter. Initialization software may, at the same time, optionally reconfigure counter
2 to use one of the three prescale taps so that the E-clock is divided by 2, 4, or 8 before driving the
free-running counter, and may select the falling, rising or both edges of an external clock. If counter
2 uses the external clock, then the prescaler bits have no effect.
6.1.3
Input Capture Functions
The fixed input capture registers (TIC1 – TIC3) are 16-bit read-only registers which are not affected
by reset and are used to latch the value of the free-running counter when a defined transition is
sensed by the corresponding input capture edge detector. They optionally cause an interrupt in
response to a detected edge event on an input pin. Pairs of bits in the TCTL2 register allow the user
to specify that input capture will occur on rising edges only, falling edges only, rising and falling edges
or to inhibit captures completely. Registers TMSK1 and TFLG1 provide interrupt enable and
interrupt flag bits, respectively Input captures IC1 – IC3 are associated with Port A, bits 2 – 0,
respectively.
6.1.4
Output Compare Functions
The fixed output compare registers (TOC1 – TOC4) are 16-bit read/write registers which are
initialized to $FFFF by reset and can be used for several purposes. Possible applications include
controlling an output waveform and indicating when a period of time has elapsed. The output
compare registers are unique in that all bits are readable and writable and are not altered by the timer
hardware (except during reset). If an output compare function is not utilized, the unused registers
may be used simply as storage locations. Output compares OC1 – OC4 are associated with
Port A bits 7 – 4, respectively.
The output compare functions referred to above cause an output action and/or an interrupt when
there is a match between a 16-bit output compare register and the free-running counter. At any time
the bits controlled by the output compare functions may be read to determine the current state of
the output pin.
Three of the fixed output compare functions (OC2, OC3 and OC4) and all of the programmable ones
allow software to specify that the corresponding output pin should toggle, be set to one, be cleared
to zero, or be disconnected from the output pin logic. This is controlled using the OMx and OML bits
in the timer control registers TCTL1 and TCTL3.
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