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參數(shù)資料
| 型號(hào)： | MC68HC711G5CFN |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁(yè)數(shù)： | 154/195頁(yè) |
| 文件大小： | 1940K |
| 代理商： | MC68HC711G5CFN |
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RESETS, INTERRUPTS AND LOW POWER MODES
5-9
5.2.5
Interrupt Mask Bits in Condition Code Register
On reset, both the X bit and the I bit in the CCR are set to inhibit all maskable interrupts and XIRQ.
After minimum system initialization, software may clear the X bit by a TAP instruction, thus enabling
XIRQ interrupts. Thereafter, software cannot set the X bit. Thus, an XIRQ is effectively a non-
maskable interrupt. Since the operation of the I bit related interrupt structure has no effect on the
X bit, the internal XIRQ pin remains effectively non-masked. In the interrupt priority logic, the XIRQ
interrupt is a higher priority than any source that is maskable by the I bit. All I bit related interrupts
operate normally with their own priority relationships.
When an I bit related interrupt occurs, the I bit is automatically set by hardware after stacking the
CCR byte. The X bit is not affected. When an X bit related interrupt occurs, both the X and the I bit
are automatically set by hardware after stacking the CCR byte. A return from interrupt (RTI)
instruction restores the X and I bits to their pre-interrupt request state.
5.2.6
Priority and Masking Structure
Interrupts obey a fixed hardware priority circuit to resolve simultaneous requests. However, one I bit
related interrupt source may be elevated to the highest I bit priority position in the resolution circuit.
Six interrupt sources are not masked by the I bit in the condition codes register and have the fixed
priority relationship:
1.
Reset
2.
Clock failure monitor
3.
COP failure
4.
Illegal opcode
5.
SWI
6.
XIRQ
SWI is actually an instruction and has highest priority other than reset in the sense that once the SWI
opcode is fetched, no other interrupt can be honoured until after the first instruction in the SWI
service routine has been executed. The scenario is similar for the illegal opcode.
Each of these sources is an input to the priority resolution circuit. The highest I bit masked priority
input to the resolution circuit is assigned under software control (via the HPRIO register) to be
connected to any one of the remaining I bit related interrupt sources. In order to avoid timing races
the HPRIO register may only be written while the I bit related interrupts are inhibited (I bit in CCR
set). An interrupt which is assigned to this high priority position is still subject to masking by any
associated control bits or by the I bit in the CCR. The address from which the interrupt vector is
fetched is not affected by assigning a source to this higher priority position.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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| MC68HC711K4CFN4 | 功能描述:IC MCU 24K OTP 4MHZ 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC11 標(biāo)準(zhǔn)包裝:250 系列:56F8xxx 核心處理器:56800E 芯體尺寸:16-位 速度:60MHz 連通性:CAN，SCI，SPI 外圍設(shè)備:POR，PWM，溫度傳感器，WDT 輸入/輸出數(shù):21 程序存儲(chǔ)器容量:40KB（20K x 16） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:6K x 16 電壓 - 電源 (Vcc/Vdd):2.25 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 6x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:48-LQFP 包裝:托盤 配用:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323 |
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| MC68HC711K4CFNE4 | 制造商:Freescale Semiconductor 功能描述: |
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