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| 型號： | MC68HC711G5CFN |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 167/195頁 |
| 文件大小： | 1940K |
| 代理商： | MC68HC711G5CFN |
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PROGRAMMABLE TIMER
6-3
Unlike the other output compare functions, OC1 can automatically affect any or all of the Port A
output pins associated with OC2 – OC5 (with OC5/IC4 configured for output compare), as a result
of a successful compare between the OC1 register and the 16-bit free running counter. Two 5-bit
registers are used in conjunction with this function, the output compare 1 mask register (OC1M) and
the output compare 1 data register (OC1D). The OC1M register specifies bit-for-bit which Port A
lines (bits 3 – 7) are to be affected and the OC1D register specifies what data is to be placed on the
affected lines. By configuring the system so that both OC1 and another output compare function both
control the same output line, output pulses can be generated with durations as short as one free
running counter count.
Since the four other output compare functions (OC2 – OC5) optionally affect four bits of Port A and
the pulse accumulator optionally uses bit 7 of Port A, there is an overlap of these functions with the
OC1 output compare function. Pins are made available to the OC1 function when other timer
functions are not used or are used in a manner that does not require use of the I/O pin.
A write-only register (CFORC) is provided to allow the equivalent of a forced output compare
function. Writing a one to any bit in this register immediately has the same effect as a successful
comparison on the corresponding output compare function.
In some cases the values in the output compare register and the output action control bits must be
changed after each successful comparison to control an output waveform or to establish a new
elapsed timeout.
Due to the prescaler, the counter may not change value on each cycle of the E-clock and the
comparison may be true for several consecutive E-clock cycles. In order to avoid multiple output
actions, the output action is permitted to occur only during the E-clock low time immediately following
the cycle during which the match first became true.
An interrupt can also accompany a successful output compare provided that the corresponding
interrupt enable bit (OCxI) in the TMSK1 register is set. In this event, the corresponding interrupt
flag bit (OCxI) in the TFLG1 register will be set.
After writing to the TOCx register’s most significant byte, the output compare function is inhibited
for one E-clock cycle, to allow writing two consecutive bytes before making the next comparison.
If both bytes of the register are to be changed, a double byte write instruction should be used in order
to take advantage of the compare inhibit feature.
MPU writes can be made to either byte of the output compare register without affecting the other
byte. When a compare occurs, the output action is taken regardless of whether or not the output
compare flag (OCxF) was previously set.
6.1.5
Programmable Input Capture/Output Compares
There are three programmable input capture/output compares. Each channel has a 16-bit register
(TO5I4, TO6I5, TO7I6) associated with it which acts as either an output compare register or an
input capture register depending on which is specified. OC5/IC4 and OC6/IC5 are associated
with counter 1 and OC7/IC6 is associated with counter 2. The selection of output compare or
input capture for these functions is controlled by the I4/O5 bit in the PACTL register and the I5/O6
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For More Information On This Product,
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