
NON-DISCLOSURE
AGREEMENT
REQUIRED
Serial Communications Interface Module (SCI)
Advance Information
MC68HC(9)08LJ60 — Rev. 1.0
186
Serial Communications Interface Module (SCI)
MOTOROLA
12.4.3.2 Character Reception
During an SCI reception, the receive shift register shifts characters in
from the RxD pin. The SCI data register (SCDR) is the read-only buffer
between the internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data
portion of the character transfers to the SCDR. The SCI receiver full bit,
SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the
received byte can be read. If the SCI receive interrupt enable bit, SCRIE,
in SCC2 is also set, the SCRF bit generates an SCRF CPU interrupt
request.
12.4.3.3 Data Sampling
The receiver samples the RxD pin at the RT clock rate. The RT clock is
an internal signal with a frequency 16 times the baud-rate frequency.
Start bit — To locate the start bit, recovery logic does an
asynchronous search for a logic 0 preceded by three logic 1s.
When the falling edge of a possible start bit occurs, the RT clock
begins to count to 16.
To verify a valid start bit, data recovery logic takes samples at
RT3, RT5, and RT7. If any two of these three samples are logic
1s, the RT clock is reset and the search for start bit begins again.
If all three samples are logic 0s, start bit verification is successful.
If only one of the three samples is logic 1, start bit verification is
successful, but the noise flag (NF) becomes set.
Data bit — To detect noise in data bits, recovery logic takes
samples at RT8, RT9, and RT10 of every data bit time. If all three
samples are not unanimous, the noise flag becomes set.
Stop bit — To detect noise in stop bits, recovery logic takes
samples at RT8, RT9, and RT10. If all three samples are not
unanimous, the noise flag becomes set.
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.