
NON-DISCLOSURE
AGREEMENT
REQUIRED
External Interrupt Module (IRQ)
Advance Information
MC68HC(9)08LJ60 — Rev. 1.0
170
External Interrupt Module (IRQ)
MOTOROLA
11.4.1 IRQ1 Pin
A logic 0 on the IRQ1 pin can latch an interrupt request into the IRQ1
latch. A vector fetch, software clear, or reset clears the IRQ1 latch.
If the MODE1 bit is set, the IRQ1 pin is both falling-edge-sensitive and
low-level-sensitive. With MODE1 set, both of these actions must occur
to clear the IRQ1 latch:
Vector fetch, software clear, or reset — A vector fetch generates
an interrupt acknowledge signal to clear the latch. Software may
generate the interrupt acknowledge signal by writing a logic 1 to
the ACK1 bit in the interrupt status and control register (ISCR).
The ACK1 bit is useful in applications that poll the IRQ1 pin and
require software to clear the IRQ1 latch. Writing to the ACK1 bit
can also prevent spurious interrupts due to noise. Setting ACK1
does not affect subsequent transitions on the IRQ1 pin. A falling
edge that occurs after writing to the ACK1 bit latches another
interrupt request. If the IRQ1 mask bit, IMASK1, is clear, the CPU
loads the program counter with the vector address at locations
$FFFA and $FFFB.
Return of the IRQ1 pin to logic 1 — As long as the IRQ1 pin is at
logic 0, the IRQ1 latch remains set.
The vector fetch or software clear and the return of the IRQ1 pin to logic
1 may occur in any order. The interrupt request remains pending as long
as the IRQ1 pin is at logic 0.
If the MODE1 bit is clear, the IRQ1 pin is falling-edge-sensitive only.
With MODE1 clear, a vector fetch or software clear immediately clears
the IRQ1 latch.
Use the BIH or BIL instruction to read the logic level on the IRQ1 pin.
NOTE:
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
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