
External Interrupt Module (IRQ)
Functional Description
MC68HC(9)08LJ60 — Rev. 1.0
Advance Information
MOTOROLA
External Interrupt Module (IRQ)
171
NON-DISCLOSURE
AGREEMENT
REQUIRED
11.4.2 IRQ2 Pin
When the IRQ2DIS bit is clear, a logic 0 on the IRQ2 pin can latch an
interrupt request into the IRQ2/keyboard interrupt latch. A vector fetch,
software clear, or reset clears the IRQ2/keyboard interrupt latch.
If the MODE2 bit is set, the IRQ2 pin is both falling-edge-sensitive and
low-level-sensitive. With MODE2 set, both of these actions must occur
to clear the IRQ2 interrupt latch:
Vector fetch, software clear, or reset — A vector fetch generates
an interrupt acknowledge signal to clear the latch. Software may
generate the interrupt acknowledge signal by writing a logic 1 to
the ACK2 bit in the interrupt status and control register (ISCR).
The ACK2 bit is useful in applications that poll the IRQ2 pin and
require software to clear the IRQ2 interrupt latch. Writing to the
ACK2 bit can also prevent spurious interrupts due to noise. Setting
ACK2 does not affect subsequent transitions on the IRQ2 pin. A
falling edge that occurs after writing to the ACK2 bit latches
another interrupt request. If the IRQ2 mask bit, IMASK2, is clear,
the CPU loads the program counter with the vector address at
locations $FFD2 and $FFD3.
Return of the IRQ2 pin to logic 1 — As long as the IRQ2 pin is at
logic 0, the IRQ2 interrupt latch remains set.
The vector fetch or software clear and the return of the IRQ2 pin to logic
1 may occur in any order. The interrupt request remains pending as long
as the IRQ2 pin is at logic 0.
If the MODE2 bit is clear, the IRQ2 pin is falling-edge-sensitive only.
With MODE2 clear, a vector fetch or software clear immediately clears
the IRQ2 interrupt latch.
To determine the logic level on the IRQ2 pin, read the IRQ2 pin state bit,
PIN2, in the ISCR. This bit reflects the value of the IRQ2 pin, even when
NOTE:
information about keyboard interrupt.
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