
Central Processor Unit (CPU)
Instruction Set Summary
MC68HC(9)08LJ60 — Rev. 1.0
Advance Information
MOTOROLA
Central Processor Unit (CPU)
77
NON-DISCLOSURE
AGREEMENT
REQUIRED
DBNZ
opr,rel
DBNZA
rel
DBNZX
rel
DBNZ
opr,X,rel
DBNZ X
,rel
DBNZ
opr,SP,rel
Decrement and Branch if Not Zero
A
← (A) – 1 or M ← (M) – 1 or X ← (X)–1
PC
← (PC) + 3 + rel ? (result) ≠ 0
PC
← (PC) + 2 + rel ? (result) ≠ 0
PC
← (PC) + 2 + rel ? (result) ≠ 0
PC
← (PC) + 3 + rel ? (result) ≠ 0
PC
← (PC) + 2 + rel ? (result) ≠ 0
PC
← (PC) + 4 + rel ? (result) ≠ 0
––––––
DIR
INH
IX1
IX
SP1
3B
4B
5B
6B
7B
9E6B
dd rr
rr
ff rr
rr
ff rr
5
3
5
4
6
DEC
opr
DECA
DECX
DEC
opr,X
DEC ,X
DEC
opr,SP
Decrement
M
← (M) – 1
A
← (A) – 1
X
← (X) – 1
M
← (M) – 1
M
← (M) – 1
M
← (M) – 1
¤ –– ¤¤ –
DIR
INH
IX1
IX
SP1
3A
4A
5A
6A
7A
9E6A
dd
ff
4
1
4
3
5
DIV
Divide
A
← (H:A)/(X)
H
← Remainder
–––– ¤¤ INH
52
7
EOR #
opr
EOR
opr
EOR
opr
EOR
opr,X
EOR
opr,X
EOR ,X
EOR
opr,SP
EOR
opr,SP
Exclusive OR M with A
A
← (A
⊕ M)
0 – – ¤¤ –
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A8
B8
C8
D8
E8
F8
9EE8
9ED8
ii
dd
hh ll
ee ff
ff
ee ff
2
3
4
3
2
4
5
INC
opr
INCA
INCX
INC
opr,X
INC ,X
INC
opr,SP
Increment
M
← (M) + 1
A
← (A) + 1
X
← (X) + 1
M
← (M) + 1
M
← (M) + 1
M
← (M) + 1
¤ –– ¤¤ –
DIR
INH
IX1
IX
SP1
3C
4C
5C
6C
7C
9E6C
dd
ff
4
1
4
3
5
JMP
opr
JMP
opr
JMP
opr,X
JMP
opr,X
JMP ,X
Jump
PC
← Jump Address
– – – – – –
DIR
EXT
IX2
IX1
IX
BC
CC
DC
EC
FC
dd
hh ll
ee ff
ff
2
3
4
3
2
JSR
opr
JSR
opr
JSR
opr,X
JSR
opr,X
JSR ,X
Jump to Subroutine
PC
← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP
← (SP) – 1
Push (PCH); SP
← (SP) – 1
PC
← Unconditional Address
––––––
DIR
EXT
IX2
IX1
IX
BD
CD
DD
ED
FD
dd
hh ll
ee ff
ff
4
5
6
5
4
LDA #
opr
LDA
opr
LDA
opr
LDA
opr,X
LDA
opr,X
LDA ,X
LDA
opr,SP
LDA
opr,SP
Load A from M
A
← (M)
0 – – ¤¤ –
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A6
B6
C6
D6
E6
F6
9EE6
9ED6
ii
dd
hh ll
ee ff
ff
ee ff
2
3
4
3
2
4
5
LDHX #
opr
LDHX
opr
Load H:X from M
H:X
← (M:M + 1)
0–– ¤¤ –
IMM
DIR
45
55
ii jj
dd
3
4
LDX #
opr
LDX
opr
LDX
opr
LDX
opr,X
LDX
opr,X
LDX ,X
LDX
opr,SP
LDX
opr,SP
Load X from M
X
← (M)
0 – – ¤¤ –
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
AE
BE
CE
DE
EE
FE
9EEE
9EDE
ii
dd
hh ll
ee ff
ff
ee ff
2
3
4
3
2
4
5
Table 5-1. Instruction Set Summary (Continued)
Source
Form
Operation
Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
VH I N Z C
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