
FLASH Memory
FLASH2 Functional Description
MC68HC(9)08LJ60 — Rev. 1.0
Advance Information
MOTOROLA
FLASH Memory
53
NON-DISCLOSURE
AGREEMENT
REQUIRED
When programming the FLASH, just enough program time must be
utilized via an iterative programming algorithm. Too much program time
can result in a disturb condition in which an erased bit becomes
programmed. This can be prevented as long as no more than eight
program operations are performed per row before again performing an
erase operation. Each programmed page is read in margin mode to
ensure that the bits are programmed enough for data retention over the
device’s lifetime. The row architecture for this array is:
4.4 FLASH2 Functional Description
The FLASH2 memory array contains 28,672 bytes. An erased bit reads
as a logic 0 and a programmed bit reads as a logic 1. Program and erase
operations are facilitated through control bits in a memory mapped
register. Details for these operations appear later in this section.
Memory in the FLASH array is organized into pages and rows. There are
eight pages of memory per row, and for this array, there are eight bytes
per page. The minimum erase block size is a single row, 64 bytes.
Programming is performed on a per page basis, or for this array, eight
bytes at a time. Address range for the 28-Kbyte FLASH memory is
$1000–$7FFF.
When programming the FLASH, just enough program time must be
utilized via an iterative programming algorithm. Too much program time
can result in a disturb condition in which an erased bit becomes
programmed. This can be prevented as long as no more than eight
program operations are performed per row before again performing an
erase operation. Each programmed page is read in margin mode to
ensure that the bits are programmed enough for data retention over the
device’s lifetime.
$8000–$803F
Row 0
$8040–$807F
Row 1
$8080–$80BF
Row 2
↓↓
$FFD0–$FFFF
Row 504
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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