
NON-DISCLOSURE
AGREEMENT
REQUIRED
Central Processor Unit (CPU)
Advance Information
MC68HC(9)08LJ60 — Rev. 1.0
76
Central Processor Unit (CPU)
MOTOROLA
BSET
n,opr
Set Bit
n in M
Mn
← 1
––––––
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
4
BSR
rel
Branch to Subroutine
PC
← (PC) + 2; push (PCL)
SP
← (SP) – 1; push (PCH)
SP
← (SP) – 1
PC
← (PC) + rel
– – – – – – REL
AD
rr
4
CBEQ
opr,rel
CBEQA #
opr,rel
CBEQX #
opr,rel
CBEQ
opr,X+,rel
CBEQ X+
,rel
CBEQ
opr,SP,rel
Compare and Branch if Equal
PC
← (PC) + 3 + rel ? (A) – (M) = $00
PC
← (PC) + 3 + rel ? (A) – (M) = $00
PC
← (PC) + 3 + rel ? (X) – (M) = $00
PC
← (PC) + 3 + rel ? (A) – (M) = $00
PC
← (PC) + 2 + rel ? (A) – (M) = $00
PC
← (PC) + 4 + rel ? (A) – (M) = $00
––––––
DIR
IMM
IX1+
IX+
SP1
31
41
51
61
71
9E61
dd rr
ii rr
ff rr
rr
ff rr
5
4
5
4
6
CLC
Clear Carry Bit
C
← 0
– – – – – 0 INH
98
1
CLI
Clear Interrupt Mask
I
← 0
– – 0 – – – INH
9A
2
CLR
opr
CLRA
CLRX
CLRH
CLR
opr,X
CLR ,X
CLR
opr,SP
Clear
M
← $00
A
← $00
X
← $00
H
← $00
M
← $00
M
← $00
M
← $00
0––01–
DIR
INH
IX1
IX
SP1
3F
4F
5F
8C
6F
7F
9E6F
dd
ff
3
1
3
2
4
CMP #
opr
CMP
opr
CMP
opr
CMP
opr,X
CMP
opr,X
CMP ,X
CMP
opr,SP
CMP
opr,SP
Compare A with M
(A) – (M)
¤ –– ¤¤¤
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A1
B1
C1
D1
E1
F1
9EE1
9ED1
ii
dd
hh ll
ee ff
ff
ee ff
2
3
4
3
2
4
5
COM
opr
COMA
COMX
COM
opr,X
COM ,X
COM
opr,SP
Complement (One’s Complement)
M
← (M) = $FF – (M)
A
← (A) = $FF – (M)
X
← (X) = $FF – (M)
M
← (M) = $FF – (M)
M
← (M) = $FF – (M)
M
← (M) = $FF – (M)
0–– ¤¤ 1
DIR
INH
IX1
IX
SP1
33
43
53
63
73
9E63
dd
ff
4
1
4
3
5
CPHX #
opr
CPHX
opr
Compare H:X with M
(H:X) – (M:M + 1)
¤ –– ¤¤¤ IMM
DIR
65
75
ii ii+1
dd
3
4
CPX #
opr
CPX
opr
CPX
opr
CPX ,X
CPX
opr,X
CPX
opr,X
CPX
opr,SP
CPX
opr,SP
Compare X with M
(X) – (M)
¤ –– ¤¤¤
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A3
B3
C3
D3
E3
F3
9EE3
9ED3
ii
dd
hh ll
ee ff
ff
ee ff
2
3
4
3
2
4
5
DAA
Decimal Adjust A
(A)10
U– – ¤¤¤ INH
72
2
Table 5-1. Instruction Set Summary (Continued)
Source
Form
Operation
Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
VH I N Z C
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