
NON-DISCLOSURE
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REQUIRED
Timer Interface Module (TIM)
Advance Information
MC68HC(9)08LJ60 — Rev. 1.0
270
Timer Interface Module (TIM)
MOTOROLA
value in an output compare interrupt routine (at the end of the
current pulse) could cause two output compares to occur in the
same counter overflow period.
16.4.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare
channel whose output appears on the TCH0 pin. The timer channel
registers of the linked pair alternately control the output.
Setting the MS0B bit in timer channel 0 status and control register
(TSC0) links channel 0 and channel 1. The output compare value in the
timer channel 0 registers initially controls the output on the TCH0 pin.
Writing to the timer channel 1 registers enables the timer channel 1
registers to synchronously control the output after the timer overflows. At
each subsequent overflow, the timer channel registers (0 or 1) that
control the output are the ones written to last. TSC0 controls and
monitors the buffered output compare function, and timer channel 1
status and control register (TSC1) is unused. While the MS0B bit is set,
the channel 1 pin, TCH1, is available as a general-purpose I/O pin.
Channels 2 and 3 can be linked to form a buffered output compare
channel whose output appears on the TCH2 pin. The timer channel
registers of the linked pair alternately control the output.
Setting the MS2B bit in timer channel 2 status and control register
(TSC2) links channel 2 and channel 3. The output compare value in the
timer channel 2 registers initially controls the output on the TCH2 pin.
Writing to the timer channel 3 registers enables the timer channel 3
registers to synchronously control the output after the timer overflows. At
each subsequent overflow, the timer channel registers (2 or 3) that
control the output are the ones written to last. TSC2 controls and
monitors the buffered output compare function, and timer channel 3
status and control register (TSC3) is unused. In buffered output compare
operation, do not write new output compare values to the currently active
channel registers. Writing to the active channel registers is the same as
generating unbuffered output compares.
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Freescale Semiconductor, Inc.
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