參數(shù)資料
型號： MC68HC05JB3JDW
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDSO28
封裝： SOIC-28
文件頁數(shù)： 85/148頁
文件大小： 1600K
代理商： MC68HC05JB3JDW
November 5, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05JB3
RESETS
MOTOROLA
REV 1
5-3
The POR will generate the RST signal which will reset the CPU. If any other reset
function is active at the end of the 224 or 4064 cycle delay, the RST signal will
remain in the reset condition until the other reset condition(s) end.
POR will not activate the pulldown device on the RESET pin. VDD must drop
below VPOR in order for the internal POR circuit to detect the next rise of VDD.
5.3.2 USB Reset
The USB reset is generated by a detection on the USB bus reset signal. For
MC68HC05JB3, seeing a single-end zero on its upstream port for 4 to 8 bit times
will set RSTF bit in UIR0 register. The detections will also generate the RST signal
to reset the CPU and other peripherals in the MCU.
5.3.3 Computer Operating Properly (COP) Reset
The COP watchdog is enabled by a mask option.
A timeout of the COP watchdog generates a COP reset. The COP watchdog is
part of a software error detection system and must be cleared periodically to start
a new timeout period. To clear the COP watchdog and prevent a COP reset, write
a logic zero to the COPC bit of the COP register at location $1FF0.
COPC — COP Clear
COPC is a write-only bit. Periodically writing a logic zero to COPC prevents the
COP watchdog from resetting the MCU. Reset clears the COPC bit.
1 =
No effect on system.
0 =
Reset COP watchdog timer.
The COP Watchdog reset will assert the pull-down device to pull the RESET pin
low for one cycle of the internal bus clock.
Refer to section on Multi-Function Timer for detail on COP watchdog timeout peri-
ods.
5.3.4 Low Voltage Reset (LVR)
The LVR activates the RST reset signal to reset the device when the voltage on
the VDD pin falls below the LVR trip voltage. The LVR will assert the pulldown
device to pull the RESET pin low one cycle of the internal bus clock. The Low Volt-
age Reset circuit is enabled by a mask option.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
COPR
R
00000000
$1FF0
W
COPC
reset:
UUUUUUU
0
U = UNAFFECTED BY RESET
Figure 5-2. COP Watchdog Register (COPR)
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