參數(shù)資料
型號： MC68HC05JB3JDW
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDSO28
封裝： SOIC-28
文件頁數(shù)： 144/148頁
文件大?。?/td> 1600K
代理商： MC68HC05JB3JDW
November 5, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05JB3
UNIVERSAL SERIAL BUS MODULE
MOTOROLA
REV 1
10-27
End of Transaction interrupts signify a completed transaction (receive or
transmit)
Resume interrupts signify that the USB bus is reactivated after having
been suspended
End of Packet interrupts signify that a low speed end of packet signal
was detected
All USB interrupts share the same interrupt vector. Firmware is responsible for
determining which interrupt is active.
10.6.1 USB End of Transaction Interrupt
There are three possible end of transaction interrupts: Endpoint 0 Receive,
Endpoint 0 Transmit, and a shared Endpoint 1 or Endpoint 2 Transmit. End of
transaction interrupts occur as detailed in the following sections.
10.6.1.1 Receive Control Endpoint 0
For a Control OUT transaction directed at Endpoint 0, the USB module will
generate an interrupt by setting the RXD0F ag in the UIR0 register. The
conditions necessary for the interrupt to occur are shown in the owchart of
SETUP transactions cannot be stalled by the USB function. A SETUP received by
a control endpoint will clear the STALL0 bit if it is set. The conditions for receiving
a SETUP interrupt are shown in Figure 10-30.
10.6.1.2 Transmit Control Endpoint 0
For a Control IN transaction directed at Endpoint 0, the USB module will generate
an interrupt by setting the TXD0F ag in the UIR0 register. The conditions
necessary for the interrupt to occur are shown in the owchart of Figure 10-31.
10.6.1.3 Transmit Endpoint 1 and Transmit Endpoint 2
Transmit Endpoints 1 and 2 share their interrupt ag. For an IN transaction
directed at Endpoint 1 or 2, the USB module will generate an interrupt by setting
the TXD1F ag in the UIR1 register. The conditions necessary for the interrupt to
occur are shown in the owchart of Figure 10-32.
10.6.2 Resume Interrupt
The USB module will generate a USB interrupt if low speed bus activity is
detected after entering the suspend state. A transition of the USB data lines to the
non-idle state (“K” state) while in the suspend mode will set the RESUMF ag in
the UIR1 register. There is no interrupt enable bit for this interrupt source and an
interrupt will be executed if the I bit in the CCR is cleared. A resume interrupt can
only occur while the MC68HC05JB3 is in the suspend mode.
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