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參數(shù)資料
| 型號(hào)： | MC68HC05JB3JDW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁(yè)數(shù)： | 143/148頁(yè) |
| 文件大?。?/td> | 1600K |
| 代理商： | MC68HC05JB3JDW |
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GENERAL RELEASE SPECIFICATION
November 5, 1998
MOTOROLA
UNIVERSAL SERIAL BUS MODULE
MC68HC05JB3
10-26
REV 1
RPSIZ3-RPSIZ0 — Endpoint 0 Receive Data Packet Size
These read only bits store the number of data bytes received for the last OUT
or SETUP transaction for Endpoint 0. These bits are not affected by reset.
10.5.8 USB Endpoint 0 Data Registers (UE0D0-UE0D7)
UE0RD7 - UE0RD0 — Endpoint 0 Receive Data Buffer
These read only bits are serially loaded with OUT token or SETUP token data
received over the USB’s D+ and D– pins.
UE0TD7 - UE0TD0 — Endpoint 0 Transmit Data Buffer
These write only buffers are loaded by software with data to be sent on the
USB bus on the next IN token directed at Endpoint 0.
10.5.9 USB Endpoint 1/Endpoint 2 Data Registers (UE1D0-UE1D7)
UE1TD7 - UE1TD0 — Endpoint 1/ Endpoint 2 Transmit Data Buffer
These write only buffers are loaded by software with data to be sent on the
USB bus on the next IN token directed at Endpoint 1 or Endpoint 2. These buff-
ers are shared by Endpoints 1 and 2 and depend on proper conguration of the
ENDADD bit.
10.6
USB INTERRUPTS
The USB module is capable of generating interrupts and causing the CPU to
execute the USB interrupt service routine. There are three types of USB
interrupts:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
UE0D0
R
UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
$0020
W
UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
to
::::::::
UE0D7
R
UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
$0027
W
UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
reset:
XXXXXXXX
Figure 10-27. USB Endpoint 0 Data Register (UE0D0-UE0D7)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
UE1D0
R
$0028
W
UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
to
::::::::
UE1D7
R
$002F
W
UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
reset:
XXXXXXXX
Figure 10-28. USB Endpoint 1/Endpoint2 Data Registers (UE1D0-UE1D7)
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