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參數(shù)資料
| 型號： | MC68HC05F32CFU |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.789 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數(shù)： | 45/198頁 |
| 文件大?。?/td> | 2335K |
| 代理商： | MC68HC05F32CFU |
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MC68HC05F32
MOTOROLA
14-7
RESETS AND INTERRUPTS
14
14.2.3.3
Keyboard interrupt
When congured as input pins, all eight port A lines provide a wired-OR keyboard interrupt facility
and will generate an interrupt, provided that the keyboard interrupt enable bit (KIE) in the
keyboard/timer register (KEY/TIM) is set. The address of the interrupt service routine is specied
by the contents of memory locations $0FFA and $0FFB. Since this interrupt vector is shared with
the IRQ external interrupt function the interrupt service routine should check KSF to determine the
interrupt source. KSF should be cleared by software in the interrupt service routine. Care must be
taken to allow adequate time for switch debounce before clearing the ag.
14.2.3.4
Low voltage interrupt
There is a low voltage interrupt ag that causes an interrupt whenever it is set and enabled. The
low voltage interrupt enable bit and the interrupt ag are located in the system option register
(SOR). This interrupt will vector to the service routine, located at the address specied by the
contents of memory locations $FFF4 and $FFF5.
14.2.3.5
Serial peripheral interface (SPI) interrupt
An interrupt in the serial peripheral interface (SPI) occurs when one of the interrupt ag bits in the
SPI status register SPSR is set, provided the I-bit in the condition code register is clear and the
enable bit SPIE in the SPI control register is enabled. The SPI interrupt causes the program to
vector to memory location $FFF2 and $FFF3 which contains the starting address of the interrupt
service routine. Software in the SPI service routine must determine the priority and cause of the
SPI interrupt by examined the interrupt ag bits located in the SPI status register.
14.2.3.6
Serial communications interface (SCI) interrupt
There are ve different interrupt ags (TDRE, TC, OR, RDRE, IDLE) that will cause an SCI
interrupt whenever they are set and enabled. These ve interrupt ags are found in the ve most
signicant bits of the SCI status register SCSR. The actual processor interrupt is generated only if
the I-bit in the condition code register is clear and the enable bit in the serial communication control
register 2 (SCCR2) is enabled. The SCI interrupt causes the program counter to vector to the
address pointed to by memory locations $FFF0–$FFF1 which contain the start address of the
interrupt service routine. Software in the SCI interrupt service routine must determine the priority
and cause of the SCI interrupt by examining the interrupt ags and the status bits in the serial
communications status register SCSR.
TPG
133
05F32Book Page 7 Tuesday, June 8, 1999 7:55 am
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC05F32CPU | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:a member of the M68HC05 family of HCMOS |
| MC68HC05F32FU | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:a member of the M68HC05 family of HCMOS |
| MC68HC05F32PU | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:a member of the M68HC05 family of HCMOS |
| MC68HC05F4 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:MECHANICAL DATA |
| MC68HC05F5 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
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