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參數(shù)資料
| 型號(hào)： | MC68HC05F32CFU |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.789 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁(yè)數(shù)： | 42/198頁(yè) |
| 文件大小： | 2335K |
| 代理商： | MC68HC05F32CFU |
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MOTOROLA
14-4
MC68HC05F32
RESETS AND INTERRUPTS
14
14.2.1
Interrupt priorities
Each potential interrupt source is assigned a priority which means that if more than one interrupt
is pending at the same time, the processor will service the one with the highest priority rst. For
example, if both an external interrupt and a timer interrupt are pending after an instruction
execution, the external interrupt is serviced rst.
14.2.2
Non-maskable software interrupt (SWI)
The software interrupt (SWI) is an executable instruction and a nonmaskable interrupt: it is
executed regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupts enabled), SWI
is executed after interrupts that were pending when the SWI was fetched, but before interrupts
generated after the SWI was fetched. The SWI interrupt service routine address is specied by the
contents of memory locations $FFFC and $FFFD.
14.2.3
Maskable hardware interrupts
If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts (internal and external) are
masked. Clearing the I-bit allows interrupt processing to occur. IRQ is software selectable as either
edge or edge-and-level sensitive (bit 3 of the system option register).
Note:
The internal interrupt latch is cleared in the rst part of the interrupt service routine;
therefore, one external interrupt pulse could be latched and serviced as soon as the I-bit
is cleared.
14.2.3.1
Real time and core timer (CTIMER) interrupts
There are two different core timer interrupt ags that cause a CTIMER interrupt whenever an
interrupt is enabled and its ag becomes set, namely RTIF and CTOF. The interrupt ags and
enable bits are located in the CTIMER control and status register (CTCSR). These interrupts will
vector to the same interrupt service routine, whose start address is contained in memory locations
$FFF8 and $FFF9 (see Section 5.2.1 and Figure 5-1).
To make use of the real time interrupt the RTIE bit must rst be set. The RTIF bit will then be set
after the specied number of counts.
To make use of the core timer overow interrupt, the CTOFE bit must rst be set. The CTOF bit will
then be set when the core timer counter register overows from $FF to $00.
TPG
130
05F32Book Page 4 Tuesday, June 8, 1999 7:55 am
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC05F32CPU | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:a member of the M68HC05 family of HCMOS |
| MC68HC05F32FU | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:a member of the M68HC05 family of HCMOS |
| MC68HC05F32PU | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:a member of the M68HC05 family of HCMOS |
| MC68HC05F4 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:MECHANICAL DATA |
| MC68HC05F5 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
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