MOTOROLA
3-2
MC68HC05F32
MEMORY AND REGISTERS
3
Figure 3-1 Memory map of the MC68HC05F32
$00 Port A data (PORTA)
$0000
Bootloader ROM
(496 bytes)
User ROM
(32256 bytes)
Unused
EEPROM
(256 bytes)
RAM
(920 bytes)
Unused
I/O
(80 bytes)
$0050
$0068
$0400
$0500
$8000
$FF00
$FFF0
$FFFF
MC68HC05F32
Stack
User vectors
(16 bytes)
$0054
LCD RAM (20 bytes)
$01 Port B data (PORTB)
$02 Port C data (PORTC)
$03 Port D data (PORTD)
$04 Port A DDR (DDRA)
$05 Port B DDR (DDRB)
$06 Port C DDR (DDRC)
$08 Ctimer control/status (CTCSR)
$09 Ctimer counter (CTCR)
$0A Port E data (PORTE)
$0B Port E DDR (DDRE)
$0C Port E control (PECR)
$0D Row freq. control (FCR)
$0E Column freq. control (FCC)
$0F Tone control (TNCR)
$10 Port F data (PORTF)
$11 Port F control (PFCR)
$12 Port G data (PORTG)
$13 Port G control (PGCR)
$14 Port H data (PORTH) (1)
$15 Port H control (PHCR)(1)
$16 Port I data (PORTI)
$17 Port I control (PICR)
$18 Port J data (PORTJ)
$19 Port J control (PJCR)
$1A Port D control (PDCR)
$1B Key control (KCR)
$1C EEPROM prog. (EEPROG)
$1E LCD control (LCD)
$20 Capture 1 high (ICR1H)
$21 Capture 1 low (ICR1L)
$22 Compare 1 high (OCR1H)
$23 Compare 1 low (OCR1L)
$24 Capture 2 high (ICR2H)
$25 Capture 2 low (ICR2L)
$26 Compare 2 high (OCR2H)
$27 Compare 2 low (OCR2L)
$28 Counter 1 high (CNTH/1)
$29 Counter 1 low (CNTL/1)
$2A Alt. counter high 1 (ACNTH/1)
$2B Alt. counter low 1 (ACNTL/1)
$2C Timer 1 control 1 (TCR1/1)
$2D Timer 1 control 2 (TCR2/1)
$2E Timer 1 status (TSR/1)
$30 Capture 3 high (ICR3H)
$31 Capture 3 low (ICR3L)
$32 Compare 3 high (OCR3H)
$33 Compare 3 low (OCR3L)
$34 Capture 4 high (ICR4H)
$35 Capture 4 low (ICR4L)
$36 Compare 4 high (OCR4H)
$37 Compare 4 low (OCR4L)
$38 Counter 2 high (CNTH/2)
$39 Counter 2 low (CNTL/2)
$3A Alt. counter high 2 (ACNTH/2)
$3B Alt. counter low 2 (ACNTL/2)
$3C Timer 2 control 1 (TCR1/2)(1)
$3D Timer 2 control 2 (TCR2/2)(1)
$3E Timer 2 status (TSR/2)(1)
$40 PWM control (PWMCR)
$41 PWM data 1 (PWMD1)
$42 PWM data 2 (PWMD2)
$43 PWM data 3 (PWMD3)
$44 SPI control (SPCR)(1)
$45 SPI status (SPSR)(1)
$46 SPI data I/O (SPDAT)(1)
$47 SCI data (SCDAT) (1)
$48 SCI control 1 (SCCR1)(1)
$49 SCI control 2 (SCCR2)(1)
$4A SCI status (SCSR)(1)
$4B SCI baud rate (BAUD) (1)
$4C CPI control/status (CPICSR)
$4D System options (SOR)
$4E A/D data (ADDATA) (1)
$4F A/D status/control (ADSCR)(1)
$07 Port D DDR (DDRD)
(1) Not applicable to 80-pin package.
– reserved
30
05F32Book Page 2 Tuesday, June 8, 1999 7:55 am