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MC68HC05BS8
M-BUS SERIAL INTERFACE
8
SRW - Slave R/W Select
1 (set)
–
Read from slave, from calling master
0 (clear) –
Write to slave from calling master.
When MAAS is set, the R/W command bit of the calling address sent from the master is latched
into this SRW bit. By checking this bit, the CPU can then select slave transmit/receive mode by
conguring MTX bit of the M-Bus Control register.
MIF - M-Bus Interrupt
1 (set)
–
An M-Bus interrupt has occurred.
0 (clear) –
An M-Bus interrupt has not occurred.
When this bit is set, an interrupt is generated to the CPU if MIEN is set. This bit is set when one
of the following events occurs:
1) Completion of one byte of data transfer. It is set at the falling edge of the 9th
clock - MCF set.
2) A match of the calling address with its own specic address in slave mode -
MAAS set.
3) A loss of bus arbitration - MAL set.
This bit must be cleared by software in the interrupt routine.
RXAK - Receive Acknowledge
1 (set)
–
No acknowledgment signal detected.
0 (clear) –
Acknowledgment signal detected after 8 bits data transmitted.
If cleared, it indicates an acknowledge signal has been received after the completion of 8 bits data
transmission on the bus. If set, no acknowledge signal has been detected at the 9th clock. This is
an active low status ag.
8.3.5
M-Bus Data I/O Register (MDR)
In master transmit mode, data written into this register is sent to the bus automatically, with the
most signicant bit out rst. In master receive mode, reading of this register initiates receiving of
the next byte data. In slave mode, the same function applies after it has been addressed.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$003D
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
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TPG
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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