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參數(shù)資料
| 型號(hào)： | MC68HC05BS8FB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁(yè)數(shù)： | 26/128頁(yè) |
| 文件大?。?/td> | 9691K |
| 代理商： | MC68HC05BS8FB |
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MC68HC05BS8
MC68HC705BS8
A
A.3
Modes of Operation
The MC68HC705BS8 also has two modes of operation – user mode and EPROM bootstrap
mode. Table A-1 shows the conditions required to enter each mode on the rising edge of RESET.
A.3.1
User Mode
The normal operating mode of the MC68HC705BS8 is the user mode. The user mode will be
entered if the RESET line is brought low, and the IRQ pin is within its normal operational range
(VSS to VDD), the rising edge of the RESET will cause the MCU to enter the user mode.
Warning: In the MC68HC705BS8, all vectors are fetched from EPROM in user mode; therefore,
the EPROM must be programmed (via the bootstrap mode) before the device is
powered up in user mode.
A.3.2
Bootstrap Mode
The bootstrap mode is provided in the MC68HC705BS8 as a mean of self-programming its
EPROM with minimal circuitry. It is entered on the rising edge of RESET if IRQ pin is at 1.8VDD
and PB6 is at logic one. RESET must be held low for 4064 cycles after POR (power-on reset).
A.4
EPROM Programming
The Program Control register (PCR) is provided for EPROM programming. The function of the
EPROM depends on the device operating mode.
Table A-1 MC68HC705BS8 Operating Mode Entry Conditions
RESET
IRQ
PB6
MODE
VSS to VDD
USER
+9V Rising Edge*
VDD
BOOTSTRAP
* Minimum hold time should be 2 clock cycles, after that it can be used as a normal IRQ function pin.
5V
9V
TPG
119
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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