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參數資料
| 型號： | MC68HC05BS8FB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數： | 60/128頁 |
| 文件大?。?/td> | 9691K |
| 代理商： | MC68HC05BS8FB |
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MC68HC05BS8
RESETS AND INTERRUPTS
5
5.1.4
Computer Operating Properly (COP) Reset
The MC68HC05BS8 contains a watchdog timer that automatically times out if this timer is not
reset (cleared) within a specic amount of time by a program reset sequence.
Note:
COP time-out is prevented by periodically writing a “0” to bit 0 of address $3FF0.
If the watchdog timer is allowed to time-out, an internal reset is generated to reset the MCU.
Because the internal reset signal is used, the MCU comes out of a COP reset in the same
operating mode as it was in when the COP time-out was generated.
The COP reset function is enabled after a reset, and it can be disabled by writing a “0” to bit 6 in
the Option register at address $001D. Once disabled, it cannot be enabled except by a reset
function.
See Section 6.2.3 for more information on the COP watchdog timer.
5.2
INTERRUPTS
The MC68HC05BS8 can be interrupted by different sources – six maskable hardware interrupt
and one non-maskable software interrupt:
Software Interrupt Instruction (SWI)
External signal on the IRQ pin
Sync Signal Processor (SSP)
Programmable Timer (TIMER)
Core Timer (CTIMER)
M-Bus Interface (MBUS)
Keyboard (KBI)
If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts (internal and external) are
disabled. Clearing the I-bit enables interrupts.
Interrupts cause the processor to save the register contents on the stack and to set the interrupt
mask (I-bit) to prevent additional interrupts. The RTI instruction causes the register contents to be
recovered from the stack and normal processing to resume.
Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but
are considered pending until the current instruction is complete. The current instruction is the one
already fetched and being operated on. When the current instruction is complete, the processor
checks all pending hardware interrupts. If interrupts are not masked (CCR I-bit clear) the
processor proceeds with interrupt processing; otherwise, the next instruction is fetched and
executed. Table 5-1 shows the relative priority of all the possible interrupt sources.
TPG
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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