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參數(shù)資料
| 型號： | MC68HC05BS8FB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 67/128頁 |
| 文件大?。?/td> | 9691K |
| 代理商： | MC68HC05BS8FB |
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MC68HC05BS8
RESETS AND INTERRUPTS
5
ICF - Input Capture Flag
This bit is set when a proper edge has been sensed by the input capture edge detector. It is
cleared by reading the TSR (with ICF set) followed by accessing the Input Capture register LSB
($0015).
OCF - Output Compare Flag
This bit is set when the Output Compare register matches the Counter register. It is cleared by
reading the TSR (with OCF set) and then accessing the Output Compare register LSB ($0017).
TOF - Timer Overow Flag
This bit is set during the counter transition from $FFFF to $0000. It is cleared by reading the TSR
(with TOF set) followed by reading the counter LSB ($0019).
All three timer interrupt ags have corresponding enable bits (ICIE, OCIE, and TOIE) found in the
Timer Control register (TCR) at location $12. Reset clears all enable bits preventing an interrupt
from occurring. The actual processor interrupt is generated only if the interrupt mask bit of the
condition code register is also cleared. When the interrupt is recognized, the current state of the
machine is pushed onto the stack and the interrupt mask bit in the condition code register is set.
This masks further interrupts until the present one is serviced. The service routine address is
specied by the contents of $FFF6 and $FFF7.
Refer to section 6.1 for detailed description of the 16-bit Counter Timer.
5.2.2.5
Core Timer Interrupts
There are two interrupt sources, TOF and RTIF bits of Multi-Function Timer Control and Status
Register. The interrupt service routine address is specied by the contents of memory location
$3FF4 and $3FF5.
CTOF - Timer Overow
1 (set)
–
CTimer counter overow has occurred.
0 (clear) –
No CTimer counter overow has occurred.
This bit is set when the 8-bit ripple counter overows from $FF to $00; a timer overow interrupt
will occur, if CTOFE is set. CTOF is cleared by writing a “0” to the bit.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
CTimer Control and Status Register $0008
CTOF
RTIF CTOFE RTIE
RT1
RT0
0000 0011
TPG
41
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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