
MOTOROLA
MC68341 USER’S MANUAL
4- 41
SET—RTC Initialization
1 = Update cycles are inhibited so that time and calendar bytes can be written
without an update occurring.
0 = Update cycle functions normally.
4.4.3 RTC Calibration Control Register (RCCR)
The RCCR contains the calibration data and sign bit for the RTC, used to compensate for
crystal frequency error. The calibration circuits add or subtract counts at the divide-by-128
stage in the oscillator divide circuit. Positive value adds counts and speeds up the clock;
negative values subtract counts and slow the clock down.
RCCR
$0CF
76543210
0
RDCLR
RCSN
RCD4
RCD3
RCD2
RCD1
RCD0
RESET:
UUUUUUUU
Supervisor Only
RDCLR—RTC Divider Clear
1 = Clears 15-bit RTC clock divider used to generate the 1Hz seconds clock.
0 = Normal divider operation
RCSN—RTC Calibration Sign Bit
1 = Positive calibration (adds to clock count)
0 = Negative calibration (subtracts from clock count)
RCD4–RCD0—RTC Calibration Data
This bit field contains the value (times 128 clock cycles) to be added to the clock count
each hour.
RCD4–RCD0—RTC Calibration Data
This bit field contains the value (times 128 clock cycles) to be added to the clock count
each hour. Valid range is 0 to 31 ($1F hex). Operation with values from $20-3F is
undefined.
At the start of each hour, the value in the calibration data field RCDx is loaded into a
counter. If the count is non-zero, the first minute is either shortened or lengthened by 128
clocks (as indicated by the RCSN sign bit), and the count is decremented. This correction
process is repeated each successive minute, until the count is exhausted. Each calibration
step has the effect of adding or subtracting 128 oscillator cycles every 117,964,800
(32768Hz
× 60 sec/min × 60 min/hr) oscillator cycles, or 1.085 PPM of adjustment per
calibration step. The 31 steps positive and negative support a total crystal frequency
adjustment range of
±33.6 PPM.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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