
10/31/95
SECTION 1: OVERVIEW
UM Rev.1.0
xii
MC68341 USER’S MANUAL
MOTOROLA
TABLE OF CONTENTS (Continued)
Paragraph
Page
Number
Title
Number
Section 6
DMA Controller Module
6.1
DMA Module Overview ........................................................................... 6-2
6.2
DMA Module Signal Definitions............................................................... 6-4
6.2.1
DMA Request (DREQ1, DREQ2) ........................................................ 6-4
6.2.2
DMA Acknowledge (DACK1,DACK2).................................................. 6-4
6.2.3
Ready (RDY1, RDY2) ......................................................................... 6-4
6.2.4
DMA Done (DONE1, DONE2)............................................................. 6-4
6.2.5
Data Transfer Complete (DTC ) ........................................................... 6-4
6.3
Transfer Request Generation.................................................................. 6-4
6.3.1
Internal Request Generation ............................................................... 6-5
6.3.1.1
Internal Request, Maximum Rate .................................................... 6-6
6.3.1.2
Internal Request, Limited Rate ........................................................ 6-6
6.3.2
External Request Generation .............................................................. 6-6
6.3.2.1
External Burst Mode ........................................................................ 6-6
6.3.2.2
External Cycle Steal Mode............................................................... 6-6
6.3.2.3
External Request With Other Modules............................................. 6-7
6.4
Data Transfer modes .............................................................................. 6-8
6.4.1
Single-Address Mode .......................................................................... 6-8
6.4.1.1
Single-Address Read ....................................................................... 6-8
6.4.1.2
Single-Address Write ....................................................................... 6-11
6.4.2
Dual-Address Mode............................................................................. 6-13
6.4.2.1
Dual-Address Read ......................................................................... 6-13
6.4.2.2
Dual-Address Write .......................................................................... 6-16
6.5
Bus Arbitration ........................................................................................ 6-19
6.6
DMA Channel Operation ......................................................................... 6-19
6.6.1
Channel Initialization and Startup........................................................ 6-19
6.6.2
Data Transfers..................................................................................... 6-20
6.6.2.1
Internal Request Transfers .............................................................. 6-20
6.6.2.2
External Request Transfers ............................................................. 6-20
6.6.3
Channel Termination ........................................................................... 6-21
6.6.3.1
Channel Termination........................................................................ 6-21
6.6.3.2
Interrupt Operation ........................................................................... 6-21
6.6.3.3
Fast Termination Option .................................................................. 6-22
6.7
Register Description................................................................................ 6-23
6.7.1
Byte Transfer Counter Register (BTC) ................................................ 6-25
6.7.2
Channel Control Register (CCR) ......................................................... 6-25
6.7.3
Channel Status Register (CSR) .......................................................... 6-29
6.7.4
Destination Address Register (DAR) ................................................... 6-30
6.7.5
Function Code Register (FCR) ............................................................ 6-31
6.7.6
Interrupt Register (INTR) ..................................................................... 6-32
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Freescale Semiconductor, Inc.
For More Information On This Product,
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