參數(shù)資料
型號(hào)： MC56F8255VLD
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 78/88頁(yè)
文件大?。?/td> 0K
描述： DSC 64K FLASH 60MHZ 44-LQFP
標(biāo)準(zhǔn)包裝： 160
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 60MHz
連通性： CAN，I²C，LIN，SCI，SPI
外圍設(shè)備： LVD，POR，PWM，WDT
輸入/輸出數(shù)： 35
程序存儲(chǔ)器容量： 64KB（32K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 4K x 16
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 1x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 44-LQFP
包裝： 管件
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Overview
Freescale Semiconductor
8
Up to 54 general-purpose I/O (GPIO) pins
— 5 V tolerant I/O
— Individual control for each pin to be in peripheral or GPIO mode
— Individual input/output direction control for each pin in GPIO mode
— Individual control for each output pin to be in push-pull mode or open-drain mode
— Hysteresis and configurable pullup device on all input pins
— Ability to generate interrupt with programmable rising or falling edge and software interrupt
— Configurable drive strength: 4 mA / 8 mA sink/source current
JTAG/EOnCE debug programming interface for real-time debugging
— IEEE 1149.1 Joint Test Action Group (JTAG) interface
— EOnCE interface for real-time debugging
2.1.6
Power Saving Features
Low-speed run, wait, and stop modes: as low as 781 Hz clock provided by OCCS and internal ROSC
Large regulator standby mode available for reducing power consumption at low-speed mode
Less than 30 s typical wakeup time from stop modes
Each peripheral can be individually disabled to save power
2.2
Award-Winning Development Environment
Processor Expert (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based software
application creation with an expert knowledge system.
The CodeWarrior Integrated Development Environment (IDE) is a sophisticated tool for code navigation, compiling, and
debugging. A complete set of evaluation modules (EVMs), demonstration board kit, and development system cards supports
concurrent engineering. Together, PE, CodeWarrior, and EVMs create a complete, scalable tools solution for easy, fast, and
efficient development.
2.3
Architecture Block Diagram
The MC56F825x/MC56F824x’s architecture appears in Figure 1 and Figure 2. Figure 1 illustrates how the 56800E system
buses communicate with internal memories and the IP bus interface as well as the internal connections among the units of the
56800E core.
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