參數(shù)資料
型號: MC56F8255VLD
廠商: Freescale Semiconductor
文件頁數(shù): 40/88頁
文件大?。?/td> 0K
描述: DSC 64K FLASH 60MHZ 44-LQFP
標準包裝: 160
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 60MHz
連通性: CAN,I²C,LIN,SCI,SPI
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 35
程序存儲器容量: 64KB(32K x 16)
程序存儲器類型: 閃存
RAM 容量: 4K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 1x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 44-LQFP
包裝: 管件
General System Control Information
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Freescale Semiconductor
45
5.7.3
Interconnection of PWM Module and ADC Module
In addition to how PWM0_EXTA, PWM1_EXTA, PWM2_EXTA, and PWM3_EXTA connect to crossbar outputs, the ADC
conversion high/low limit compare results of sample0, sample1, and sample2 are used to drive PWM0_EXTB, PWM1_EXTB,
and PWM2_EXTB, respectively. PWM3_EXTB is permanently tied to GND.
State of PWM0_EXTB:
If the ADC conversion result in SAMPLE0 is greater than the value programmed into the high limit register 0,
PWM0_EXTB is driven low.
If the ADC conversion result in SAMPLE0 is less than the value programmed into the low limit register 0,
PWM0_EXTB is driven high.
State of PWM1_EXTB:
If the ADC conversion result in SAMPLE1 is greater than the value programmed into the high limit register 1,
PWM1_EXTB is driven low.
XBAR_OUT7
ADCB
ADCB Trigger
XBAR_OUT8
DAC
12-bit DAC SYNC_IN
XBAR_OUT9
CMPA
Comparator A Window/Sample
XBAR_OUT10
CMPB
Comparator B Window/Sample
XBAR_OUT11
CMPC
Comparator C Window/Sample
XBAR_OUT12
PWM0 EXTA
eFlexPWM submodule 0 Alternate Control signal
XBAR_OUT13
PWM1 EXTA
eFlexPWM submodule 1 Alternate Control signal
XBAR_OUT14
PWM2 EXTA
eFlexPWM submodule 2 Alternate Control signal
XBAR_OUT15
PWM3 EXTA
eFlexPWM submodule 3 Alternate Control signal
XBAR_OUT16
PWM0 EXT_SYNC
eFlexPWM submodule 0 External Synchronization signal
XBAR_OUT17
PWM1 EXT_SYNC
eFlexPWM submodule 1 External Synchronization signal
XBAR_OUT18
PWM2 EXT_SYNC
eFlexPWM submodule 2 External Synchronization signal
XBAR_OUT19
PWM3 EXT_SYNC
eFlexPWM submodule 3 External Synchronization signal
XBAR_OUT20
PWM EXT_CLK
eFlexPWM External Clock signal
XBAR_OUT21
PWM FAULT0
eFlexPWM Module FAULT0
XBAR_OUT22
PWM FAULT1
eFlexPWM Module FAULT1
XBAR_OUT23
PWM FAULT2
eFlexPWM Module FAULT2
XBAR_OUT24
PWM FAULT3
eFlexPWM Module FAULT3
XBAR_OUT25
PWM FORCE
eFlexPWM External Output Force signal
XBAR_OUT26
TB0
Quad Timer B0 Input when SIM_GPS3[12] is set
XBAR_OUT27
TB1
Quad Timer B1 Input when SIM_GPS3[13] is set
XBAR_OUT28
TB2
Quad Timer B2 Input when SIM_GPS3[14] is set
XBAR_OUT29
TB3
Quad Timer B3 Input when SIM_GPS3[15] is set
Table 16. Crossbar Output Signal Assignments (continued)
XBAR_OUTn
Output to
Function
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