參數(shù)資料
型號： MC56F8255VLD
廠商： Freescale Semiconductor
文件頁數(shù)： 52/88頁
文件大?。?/td> 0K
描述： DSC 64K FLASH 60MHZ 44-LQFP
標準包裝： 160
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 60MHz
連通性： CAN，I²C，LIN，SCI，SPI
外圍設(shè)備： LVD，POR，PWM，WDT
輸入/輸出數(shù)： 35
程序存儲器容量： 64KB（32K x 16）
程序存儲器類型： 閃存
RAM 容量： 4K x 16
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 1x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 44-LQFP
包裝： 管件
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Specifications
Freescale Semiconductor
56
7.8
Power-On Reset, Low Voltage Detection Specification
7.9
Voltage Regulator Specifications
The MC56F825x/MC56F824x has two on-chip regulators. One supplies the PLL, crystal oscillator, NanoEdge placement
PWM, and relaxation oscillator. It has no external pins and therefore has no external characteristics that must be guaranteed
(other than proper operation of the device). The second regulator supplies approximately 2.5 V to the
MC56F825x/MC56F824x’s core logic. For proper operation, this regulator requires an external capacitor of 2.2 F or greater.
Ceramic and tantalum capacitors tend to provide better performance tolerances. The output voltage can be measured directly
on the VCAP pin. The specifications for this regulator appear in Table 26.
7.10
AC Electrical Characteristics
Tests are conducted using the input levels specified in Table 23. Unless otherwise specified, propagation delays are measured
from the 50% to the 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in Figure 15.
Figure 15. Input Signal Measurement References
Table 25. Power-On Reset and Low-Voltage Detection Parameters
Characteristic
Symbol
Min
Typ
Max
Unit
Low-Voltage Interrupt for 3.3 V supply1
1 When VDD drops below LVI27, an interrupt is generated.
VLVI27
2.6
2.7
2.8
V
Low-Voltage Interrupt for 2.5 V supply2
2 When VDD drops below LVI21, an interrupt is generated.
VLVI21
—2.18—
V
Low-Voltage Interrupt Recovery Hysteresis
VEIH
—50
—
mV
Power-On Reset Threshold3
3 While power is ramping up, this signal remains active for as long as the internal 2.5 V is below 2.18 V or
the 3.3 V VDD voltage is below 2.7 V, no matter how long the ramp-up rate is. The internally regulated
voltage is typically 100 mV less than VDD during ramp-up until 2.5 V is reached, at which time it self-reg-
ulates.
POR
2.6
2.7
2.8
V
Brown-Out Reset Threshold4
4 Brown-Out Reset occurs whenever the internally regulated 2.5 V digital supply drops below 1.8 V.
BOR
—
1.8
1.9
V
Table 26. Regulator Parameters
Characteristic
Symbol
Min
Typical
Max
Unit
Short Circuit Current
ISS
—
900
1300
mA
Short Circuit Tolerance
(VCAP shorted to ground)
TRSC
——
30
minutes
VIH
VIL
Fall Time
Midpoint1
Low
High
90%
50%
10%
Rise Time
The midpoint is VIL + (VIH – VIL)/2.
Input Signal
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