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| 型號： | MC56F8255VLD |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 70/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | DSC 64K FLASH 60MHZ 44-LQFP |
| 標準包裝： | 160 |
| 系列： | 56F8xxx |
| 核心處理器： | 56800E |
| 芯體尺寸： | 16-位 |
| 速度： | 60MHz |
| 連通性： | CAN，I²C，LIN，SCI，SPI |
| 外圍設備： | LVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 35 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 4K x 16 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉換器： | A/D 8x12b，D/A 1x12b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 44-LQFP |
| 包裝： | 管件 |
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MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Design Considerations
Freescale Semiconductor
72
B, the internal [state-dependent] component, reflects the supply current required by certain on-chip resources only when those
resources are in use. These resources include RAM, flash memory, and the ADCs.
C, the internal [dynamic] component, is classic C*V2*F CMOS power dissipation corresponding to the 56800E core and
standard cell logic.
D, the external [dynamic] component, reflects power dissipated on-chip as a result of capacitive loading on the external pins of
the chip. This component is also commonly described as C*V2*F, although simulations on two of the I/O cell types used on the
56800E reveal that the power-versus-load curve does have a non-zero Y-intercept.
Power due to capacitive loading on output pins is (first order) a function of the capacitive load and frequency at which
the outputs change. Table 45 provides coefficients for calculating power dissipated in the I/O cells as a function of
capacitive load. In these cases, Equation 2 applies.
TotalPower =
Σ((Intercept + Slope*Cload)*frequency/10 MHz)
Eqn. 2
where:
— Summation is performed over all output pins with capacitive loads.
— Total power is expressed in mW.
—Cload is expressed in pF.
Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found to be fairly
low when averaged over a period of time.
E, the external [static] component, reflects the effects of placing resistive loads on the outputs of the device. Total all V2/R or
IV to arrive at the resistive load contribution to power. Assume V = 0.5 for the purposes of these rough calculations. For
instance, if there is a total of nine PWM outputs driving 10 mA into LEDs, then P = 8*0.5*0.01 = 40 mW.
In previous discussions, power consumption due to parasites associated with pure input pins is ignored and assumed to be
negligible.
8
Design Considerations
8.1
Thermal Design Considerations
TJ = TA + (RθJΑ x PD)
Eqn. 3
where:
The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal
performance. Unfortunately, there are two values in common usage: the value determined on a single-layer board and the value
obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which
Table 45. I/O Loading Coefficients at 10 MHz
Intercept
Slope
8 mA drive
1.3
0.11 mW/pF
4 mA drive
1.15 mW
0.11 mW/pF
TA
=
Ambient temperature for the package (oC)
RθJΑ
=
Junction-to-ambient thermal resistance (oC/W)
PD
=
Power dissipation in the package (W)
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