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參數(shù)資料
| 型號： | MC56F8255VLD |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 42/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | DSC 64K FLASH 60MHZ 44-LQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | 56F8xxx |
| 核心處理器： | 56800E |
| 芯體尺寸： | 16-位 |
| 速度： | 60MHz |
| 連通性： | CAN，I²C，LIN，SCI，SPI |
| 外圍設(shè)備： | LVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 35 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 4K x 16 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 1x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 44-LQFP |
| 包裝： | 管件 |
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Security Features
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Freescale Semiconductor
47
word ensures that the device remains secure after the next reset (caused, for example, by the device powering down). Refer to
the flash memory section of the device’s reference manual for details.
When flash security mode is enabled, the MC56F825x/MC56F824x disables the core’s EOnCE debug capabilities. Normal
program execution is otherwise unaffected.
6.2
Flash Access Lock and Unlock Mechanisms
Several methods effectively lock or unlock the on-chip flash.
6.2.1
Disabling EOnCE Access
You can read on-chip flash by issuing commands across the EOnCE port, which is the debug interface for the 56800E core. The
TCK, TMS, TDO, and TDI pins compose a JTAG interface onto which the EOnCE port functionality is mapped. When the
device boots, the chip-level JTAG port is active and provides the chip’s boundary scan capability and access to the ID register.
However, proper implementation of flash security blocks any attempt to access the internal flash memory via the EOnCE port
when security is enabled. This protection is effective when the device comes out of reset, even prior to the execution of any
code at startup.
6.2.2
Flash Lockout Recovery Using JTAG
If the device is secured, one lockout recovery mechanism is the complete erasure of the internal flash contents, including the
configuration field. The erasure disables security by clearing the protection register. This approach does not compromise
security. The entire contents of your secured code stored in flash are erased before the next reset or power-up sequence, when
security becomes disabled.
To start the lockout recovery sequence via JTAG, first shift the JTAG public instruction (LOCKOUT_RECOVERY) into the
chip-level TAP controller’s instruction register. Then shift the clock divider value into the corresponding 7-bit data register.
Finally, the TAP controller must enter the RUN-TEST/IDLE state for the lockout sequence to commence. The controller must
remain in this state until the erase sequence is complete. Refer to the device’s reference manual for details, or contact Freescale.
NOTE
After completion of the lockout recovery sequence, you must reset the JTAG TAP
controller and the device to return to normal unsecured operation. A power-on reset resets
both.
6.2.3
Flash Lockout Recovery Using CodeWarrior
You can use CodeWarrior to unlock a device by selecting the following items in the indicated sequence:
1. Debug menu
2. DSP56800E
3. Unlock Flash
You can accomplish the same task with another CodeWarrior mechanism that uses the device’s memory configuration file: the
command “Unlock_Flash_on_Connect 1” in the .cfg file.
This lockout recovery mechanism completely erases the internal flash contents, including the configuration field, thereby
disabling security (the protection register is cleared).
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