參數(shù)資料
型號： MC56F8123VFBE
廠商： Freescale Semiconductor
文件頁數(shù)： 94/140頁
文件大?。?/td> 0K
描述： IC DSP 16BIT 40MHZ 64-LQFP
標(biāo)準(zhǔn)包裝： 160
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 40MHz
連通性： SCI，SPI
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 27
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 64-LQFP
包裝： 托盤
產(chǎn)品目錄頁面： 734 (CN2011-ZH PDF)
Introduction
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
57
Preliminary
Part 5 Interrupt Controller (ITCN)
5.1 Introduction
The Interrupt Controller (ITCN) module is used to arbitrate between various interrupt requests (IRQs), to
signal to the 56800E core when an interrupt of sufficient priority exists, and to what address to jump in
order to service this interrupt.
5.2 Features
The ITCN module design includes these distinctive features:
Programmable priority levels for each IRQ
Two programmable Fast Interrupts
Notification to SIM module to restart clocks out of Wait and Stop modes
Drives initial address on the address bus after reset
For further information, see Table 4-3, Interrupt Vector Table Contents.
5.3 Functional Description
The Interrupt Controller is a slave on the IPBus. It contains registers allowing each of the 82 interrupt
sources to be set to one of four priority levels, excluding certain interrupts of fixed priority. Next, all of
the interrupt requests of a given level are priority encoded to determine the lowest numerical value of the
active interrupt requests for that level. Within a given priority level, 0 is the highest priority, while number
81 is the lowest.
5.3.1
Normal Interrupt Handling
Once the ITCN has determined that an interrupt is to be serviced and which interrupt has the highest
priority, an interrupt vector address is generated. Normal interrupt handling concatenates the VBA and the
vector number to determine the vector address. In this way, an offset is generated into the vector table for
each interrupt.
5.3.2
Interrupt Nesting
Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be
serviced. The following tables define the nesting requirements for each priority level.
Table 5-1 Interrupt Mask Bit Definition
SR[9]1
1. Core status register bits indicating current interrupt mask within the core.
SR[8]1
Permitted Exceptions
Masked Exceptions
0
Priorities 0, 1, 2, 3
None
0
1
Priorities 1, 2, 3
Priority 0
1
0
Priorities 2, 3
Priorities 0, 1
1
Priority 3
Priorities 0, 1, 2
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