參數(shù)資料
型號： MC56F8123VFBE
廠商： Freescale Semiconductor
文件頁數(shù)： 63/140頁
文件大?。?/td> 0K
描述： IC DSP 16BIT 40MHZ 64-LQFP
標準包裝： 160
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 40MHz
連通性： SCI，SPI
外圍設備： POR，WDT
輸入/輸出數(shù)： 27
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 2.25 V ~ 3.6 V
數(shù)據(jù)轉換器： A/D 8x12b
振蕩器型： 內部
工作溫度： -40°C ~ 105°C
封裝/外殼： 64-LQFP
包裝： 托盤
產品目錄頁面： 734 (CN2011-ZH PDF)
Signal Pins
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
29
Preliminary
TC0
(TXD0)
(GPIOC6)
1Schmitt
Input/
Output
Input
Schmitt
Input/
Output
Input,
pull-up
enabled
TC0 — Timer C, Channel 0
Transmit Data — SCI0 transmit data output
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is TC0.
TC1
(RXD0)
(GPIOC5)
64
Schmitt
Input/
Output
Schmitt
Input
Schmitt
Input/
Output
Input,
pull-up
enabled
TC1 — Timer C, Channel 1
Receive Data — SCI0 receive data input
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is TC1.
TC3
(GPIOC4)
63
Schmitt
Input/
Output
Schmitt
Input/
Output
Input,
pull-up
enabled
TC3 — Timer C Channel 3
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is TC3.
IRQA
(VPP)
12
Schmitt
Input
Input,
pull-up
enabled
External Interrupt Request A — The IRQA input is an
asynchronous external interrupt request during Stop and Wait mode
operation. During other operating modes, it is a synchronized
external interrupt request which indicates an external device is
requesting service. It can be programmed to be level-sensitive or
negative-edge-triggered
VPP — This pin is used for Flash debugging purposes.
RESET
2Schmitt
Input
Input,
pull-up
enabled
Reset — This input is a direct hardware reset on the processor.
When RESET is asserted low, the device is initialized and placed in
the reset state. A Schmitt trigger input is used for noise immunity.
The internal reset signal will be deasserted synchronous with the
internal clocks after a fixed number of internal clocks.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and the
JTAG/EOnCE module must not be reset. In this case, assert RESET,
but do not assert TRST.
Table 2-2 Signal and Package Information for the 64-Pin LQFP
Signal Name
Pin No.
Type
State During
Reset
Signal Description
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