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參數資料
型號: MC56F8123VFBE
廠商: Freescale Semiconductor
文件頁數: 13/140頁
文件大?。?/td> 0K
描述: IC DSP 16BIT 40MHZ 64-LQFP
標準包裝: 160
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 40MHz
連通性: SCI,SPI
外圍設備: POR,WDT
輸入/輸出數: 27
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 3.6 V
數據轉換器: A/D 8x12b
振蕩器型: 內部
工作溫度: -40°C ~ 105°C
封裝/外殼: 64-LQFP
包裝: 托盤
產品目錄頁面: 734 (CN2011-ZH PDF)
Architecture Block Diagram
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
11
Preliminary
1.4 Architecture Block Diagram
Note: Features in italics are NOT available in the 56F8123 device and are shaded in the following figures.
The 56F8323/56F8123 architecture is shown in Figure 1-1 and Figure 1-2. Figure 1-1 illustrates how the
56800E system buses communicate with internal memories and the IPBus Bridge. Table 1-2 lists the
internal buses in the 56800E architecture and provides a brief description of their function. Figure 1-2
shows the peripherals and control blocks connected to the IPBus Bridge. The figures do not show the
on-board regulator and power and ground signals. They also do not show the multiplexing between
peripherals or the dedicated GPIOs. Please see Part 2 Signal/Connection Descriptions, to see which
signals are multiplexed with those of other peripherals.
Also shown in Figure 1-2 are connections between the PWM, Timer C and ADC blocks. These
connections allow the PWM and/or Timer C to control the timing of the start of ADC conversions. The
Timer C, Channel 2, output can generate periodic start (SYNC) signals to the ADC to start its conversions.
In another operating mode, the PWM load interrupt (SYNC output) signal is routed internally to the Timer
C, Channel 2, input as indicated. The timer can then be used to introduce a controllable delay before
generating its output signal. The timer output then triggers the ADC. To fully understand this interaction,
please see the 56F8300 Peripheral User Manual for clarification on the operation of all three of these
peripherals.
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